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VXI-MXI User Manual viii © National Instruments Corporation
Figures
Figure 1-1. VXI-MXI Interface Module ............................................................................. 1-2
Figure 1-2. VXI-MXI Interface Module with INTX Option............................................... 1-3
Figure 2-1. VXI-MXI Block Diagram................................................................................. 2-6
Figure 2-2. VXI-MXI INTX Daughter Card Option Block Diagram ................................. 2-8
Figure 3-1. VXI-MXI Parts Locator Diagram..................................................................... 3-2
Figure 3-2. VXI-MXI with INTX Parts Locator Diagram .................................................. 3-3
Figure 3-3. VXIbus Slot 0 Selection ................................................................................... 3-4
Figure 3-4. VXIbus Non-Slot 0 Selection ........................................................................... 3-5
Figure 3-5. Logical Address Selection ................................................................................ 3-7
Figure 3-6. VMEbus Requester Jumper Settings ................................................................ 3-8
Figure 3-7. VMEbus Timeout Value Selection................................................................... 3-9
Figure 3-8. VMEbus Timeout; One VXI-MXI in Mainframe ............................................ 3-10
Figure 3-9. VMEbus Timeout; Multiple VXI-MXIs in Mainframe.................................... 3-11
Figure 3-10. No VMEbus Timeout; Multiple VXI-MXIs in Mainframe.............................. 3-12
Figure 3-11. Interlocked Arbitration Mode Selection ........................................................... 3-14
Figure 3-12. MXIbus System Controller Selection............................................................... 3-15
Figure 3-13. MXIbus System Controller Timeout Value Selection...................................... 3-16
Figure 3-14. MXIbus Fair Requester Selection..................................................................... 3-17
Figure 3-15. CLK10 Source Signal Options ......................................................................... 3-19
Figure 3-16. EXT CLK SMB Input/Output Setting .............................................................. 3-20
Figure 3-17. INTX CLK10 Mapping Switches..................................................................... 3-21
Figure 3-18. Trigger Input Termination Option Settings ...................................................... 3-22
Figure 3-19. Reset Signal Selection Settings ........................................................................ 3-23
Figure 3-20. MXIbus System ................................................................................................ 3-24
Figure 3-21. MXIbus Terminating Networks........................................................................ 3-25
Figure 3-22. INTX Terminator Example............................................................................... 3-26
Figure 3-23. MXIbus Single-Ended Cable Configuration .................................................... 3-28
Figure 3-24. MXIbus Dual-Ended Cable Configuration....................................................... 3-29
Figure 4-1. VXI-MXI Register Map ................................................................................... 4-3
Figure 5-1. VXIbus/MXIbus System with Multiframe RM on a PC .................................. 5-2
Figure 5-2. VXIbus/MXIbus System with Multiframe RM in a VXIbus Mainframe......... 5-2
Figure 5-3. Base and Size Combinations ............................................................................ 5-4
Figure 5-4. Address Range Allocation for Different Size Values....................................... 5-4
Figure 5-5. Example VXIbus/MXIbus System ................................................................... 5-8
Figure 5-6. Logical Address Map Diagram for Example VXIbus/MXIbus System........... 5-9
Figure 5-7. Worksheet 1 for Example VXIbus/MXIbus System ........................................ 5-10
Figure 5-8. Worksheet 2 for Example VXIbus/MXIbus System ........................................ 5-11
Figure 5-9. Worksheet 3 for Example VXIbus/MXIbus System ........................................ 5-12
Figure 5-10. Worksheet 4 for Example VXIbus/MXIbus System ........................................ 5-12
Figure 5-11. Logical Address Map Example with Alternative Worksheet ........................... 5-20
Figure 5-12. A16 Space Allocations for all Size Values....................................................... 5-22
Figure 5-13. Example VXIbus/MXIbus System ................................................................... 5-24
Figure 5-14. Example A16 Space Address Map ................................................................... 5-25
Figure 5-15. Worksheet 1 for A16 Address Map Example................................................... 5-26
Figure 5-16. Worksheet 2 for A16 Map Example................................................................. 5-27
Figure 5-17. Worksheet 3 for A16 Map Example................................................................. 5-28