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Chapter 5 Programming Considerations
© National Instruments Corporation 5-5 VXI-MXI User Manual
High/Low Configuration Format
Each address mapping window on a MXIbus interface has High and Low address parameters
associated with it when the CMODE bit in the MXIbus Control Register is set. The High and
Low values define the range of MXIbus addresses that map into the VXIbus. The High bits
define the upper bound address of the window, and the Low bits indicate the lower bound
address of the window. To map a range of addresses from the VXIbus to the MXIbus (out of the
mainframe), the RM places the upper bound of the window in the Low field, and the lower
bound of the window in the High field. The window is disabled if the upper and lower bound are
both equal to zero.
Steps to Follow When Planning a System Logical Address Map
As system integrator, when installing devices in the VXIbus/MXIbus system, you must assign a
range of logical addresses for each VXIbus mainframe and MXIbus link. The multiframe RM
configures the logical address windows of each device to include the static logical addresses it
finds in the mainframe, and returns an error if the static logical address assignments prevent
assignment of an entire system logical address map. Devices with dynamically configurable
logical addresses are assigned logical addresses within the range of addresses defined by the
static devices in the mainframe.
The example system in Figure 5-5 has two levels. The VXIbus RM is in VXIbus Mainframe #1.
Use the following steps to develop a logical address map. The example worksheets show
numbers for using Base/Size window formats. For High/Low format systems, you do not need to
round the range of addresses for each mainframe up to the next power of two. Following the
example system are worksheets you can use for analyzing your own system.
1. Lay out your system configuration and determine the number of logical addresses required
by each VXIbus mainframe and MXIbus device. See Figure 5-5 and Table 5-2 for
examples. Identify the multiframe RM and label its host device as the root of the system.
Also identify the levels of the system and the MXIbus links on each level. MXIbus links
cannot span across levels.
2. Determine the number of logical addresses required by the root device. If the RM is a PC
with a MXIbus interface, the total number of logical addresses required is 1. If the RM is in
a VXIbus mainframe, determine the number of logical addresses required by all devices in
that mainframe. Fill in that number in the appropriate space in the RM block as shown in
Figure 5-7. If you are using the Base/Size format of the windows, round that number to the
next highest power of two and place that number in the appropriate space.
Note: If your RM is a PC with a MXIbus interface and you have more than one
VXIbus mainframe on Level 1, you must change the logical addresses of both
VXI-MXI interfaces so that they are not at the default of 1. Select a logical
address that is greater than or equal to the number of logical addresses required
by the mainframe.
In the example system, the multiframe RM is installed in VXIbus Mainframe #1 and that
frame requires 12 logical addresses. We rounded the value 12 to the next highest power of
two and entered the number 16 into the table.