Filter
Top Products
Chapter 6 Theory of Operation
© National Instruments Corporation 6-13 VXI-MXI User Manual
All MXIbus masters must have bus request logic for requesting the MXIbus, and the MXIbus
System Controller must have bus arbiter logic to grant the bus to requesting masters. Four
signals are used for arbitration: bus request (BREQ*), bus grant in (BGIN*), bus grant out
(BGOUT*), and bus busy (BUSY*). The MXIbus has a serial, release-on-request arbitration
with fairness and bus lock options.
In a serial arbitration scheme, devices request the bus by asserting the BREQ* line. This signal
is a wired-OR signal that indicates when one or more MXIbus devices are requesting use of the
bus. When the System Controller detects BREQ* active, it grants the bus by driving the bus
grant daisy-chain line BGOUT* active. BGOUT* propagates down the daisy-chain to the next
device's BGIN* signal. If that device is not driving the BREQ* line, it passes the BGIN* signal
on to the next device in the daisy-chain via its BGOUT* line. The first device that is driving
BREQ* and receives an active low level on its BGIN* line is the device that is granted the bus.
That device does not pass the bus grant signal on the daisy-chain to the next device.
When a requester is granted control of the bus, it drives the BUSY* line active and unasserts
BREQ*. The BUSY* signal indicates to the other MXIbus devices that the bus is busy. The
master in control of the bus holds BUSY* low until it is finished with the bus. At that time, if no
other MXIbus device is driving BREQ*, the master can continue to drive BUSY* until it detects
the BREQ* line active.
A VXIbus device can lock the MXIbus so that the device can perform indivisible operations
across the MXIbus. When the LOCK bit in the Local Bus Lock Register is set by a VXIbus
device, the VXI-MXI interface will not release the MXIbus the next time it is granted the bus (on
the next transaction) until the LOCK bit is cleared by a VXIbus device.
A fairness feature ensures that all requesting devices will be granted use of the bus. If fairness is
enabled, a master must refrain from driving BREQ* active after releasing it until it detects
BREQ* inactive.
When the VXI-MXI is arbitrating for the MXIbus and a remote MXIbus transfer requesting the
VMEbus is received, deadlock occurs. The VXI-MXI cannot win the MXIbus because another
MXIbus device owns it, and that device wants to arbitrate for the VMEbus, which is currently
owned by another device. To resolve the conflict, the MXIbus master transfer in the process of
arbitrating for the MXIbus terminates its VMEbus transfer by sending a BERR to the VMEbus.
The remote MXIbus transfer to the VMEbus can then arbitrate for the VMEbus and complete.
Unless the optional interlocked arbitration mode is used, VXI modules must be able to handle the
BERR exceptions that occur because of deadlock conditions. In interlocked arbitration mode,
only one device owns the VXIbus/MXIbus system at a time. Deadlocks are prevented because
there is only one master of the entire system (VXIbus and MXIbus) at a time.
In interlocked arbitration mode, the VXIbus arbiter and the MXIbus arbiter are synchronized so
that both buses are tightly coupled at all times. When the VXI-MXI receives a VMEbus BGIN*
signal, it cannot drive the daisy-chain VMEbus BGOUT* signal until it owns the MXIbus (is
driving the MXIbus BUSY* signal). Similarly, when the VXI-MXI receives a MXIbus BGIN*
signal, it cannot drive the MXIbus BGOUT* lines until it owns the VMEbus (is driving the
VMEbus BBSY* signal). When the VXI-MXI is driving the VMEbus BBSY* signal, it cannot
release the line until it owns the MXIbus. Similarly, when the VXI-MXI is driving the MXIbus
BUSY* signal, it cannot release the line until it owns the VMEbus. In other words, the
VXI-MXI cannot release the bus it owns until it gains ownership of the other bus.