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Theory of Operation Chapter 6
VXI-MXI User Manual 6-4 © National Instruments Corporation
The two trigger interrupt conditions are Trigger Synchronous and Trigger Asynchronous. A
synchronous trigger interrupt occurs when the input trigger signal changes from low to high.
The asynchronous trigger interrupt occurs when the input trigger signal changes from high to
low. These interrupts can be used to receive trigger protocols.
VMEbus interrupt requests can be handled by an interrupt handler on another VMEbus device in
the VXIbus mainframe or by an external device on the MXIbus. The VXI-MXI has IACK daisy-
chain driver circuitry that passes interrupt acknowledge cycles not meant for the VXI-MXI to
other interrupters in the VXIbus mainframe. Similarly, the MXIbus has an IACK daisy-chain
mechanism that converts and passes interrupt acknowledge cycles from VMEbus to MXIbus to
VMEbus, making transparent interrupt acknowledge cycles possible between VXIbus
mainframes. Because multiple VMEbus IRQ lines can be mapped onto the single MXIbus IRQ
line, interrupt acknowledge sequences for MXIbus IRQ requests cannot be completely
transparent. You can have completely transparent interrupt handling through the use of the
INTX daughter card option, in which each VMEbus interrupt line is mapped on a separate signal.
When multiple VMEbus IRQ lines are mapped onto the single shared MXIbus IRQ line, the
interrupt handler routine can acknowledge the interrupts in one of two ways.
1. If the interrupt handler cannot perform MXIbus IACK cycles, it must poll all MXIbus
devices to determine the source of the MXIbus IRQ signal. The interrupt handler polls the
MXIbus IRQ Configuration Register and the Interrupt Status Register of each VXI-MXI on
the MXIbus link to determine which VMEbus IRQ line is being sourced onto the MXI IRQ
line. The interrupt handler can then read from the corresponding IRQ acknowledge register
on the VXI-MXI driving the MXIbus IRQ line to acknowledge the interrupt request.
2. If the interrupt handler can generate MXIbus IACK cycles, it is not necessary to poll MXIbus
devices to find the source of the MXIbus IRQ signal. The interrupt handler can perform an
IACK cycle for the VMEbus line onto which the MXIbus IRQ line is mapped in that frame.
The VXI-MXI driving the MXIbus IRQ line responds with a Status/ID value in which the
lower byte is the logical address of the VXI-MXI. The interrupt handler then polls the
MXIbus IRQ Configuration Register and the Interrupt Status Register on the VXI-MXI at the
logical address specified by the Status/ID value received to determine which VMEbus IRQ
line is routed onto the MXIbus IRQ line. The interrupt handler can then read from the
corresponding VXI-MXI IRQ acknowledge register to acknowledge the interrupt request.
When this process is completed and if another VMEbus IRQ is also driving the MXIbus IRQ, the
interrupt handler module is interrupted again, and should follow the same procedure described
above.
MXIbus defines a special interrupt acknowledge (IACK) cycle, which is denoted with a special
MXIbus address modifier code, hex 12. When a VMEbus interrupt handler generates a VMEbus
IACK cycle for an active interrupt request line that is mapped into its VXIbus mainframe from
the MXIbus IRQ line, the VMEbus IACK cycle is converted into a MXIbus IACK cycle. The
VXI-MXI driving the interrupt request initiates a VMEbus IACK cycle when it detects the
MXIbus IACK cycle, and responds by driving its Status/ID on the data bus and asserting
DTACK*. The interrupt handler receives the Status/ID and DTACK* from across the MXIbus
as if it had been in the same mainframe as the VXI-MXI.
The Status/ID information returned by the remote VXI-MXI indicates its logical address. With
this information, the interrupt handler can poll the remote VXI-MXI to determine which interrupt
lines are mapped onto the MXIbus IRQ line and which interrupt lines are active. The interrupt is
then acknowledged by reading the corresponding register shown in Table 6-1.