Filter
Top Products
Chapter 6 Theory of Operation
© National Instruments Corporation 6-7 VXI-MXI User Manual
complete when the responding device sends DTACK* and the VXI-MXI releases the data strobe
and address strobe. The VXI-MXI interface supports 8-bit, 16-bit, and 32-bit reads and writes
across the MXIbus. The least significant data bit maps to MXIbus data line AD00 and the byte
orientation on the MXIbus is standard 68000 format. Notice, however, that byte significance is
not specified by MXIbus because MXIbus devices themselves are responsible for ensuring
correct data ordering.
Communication across the MXIbus between devices in separate VXIbus mainframes appears as
normal transfers to the devices. The bus cycles are mapped from one device through the
addressing windows, across the MXIbus, and through address windows on the second device.
The first device initiates the transfer with an address strobe and data strobe, and the second
device responds by asserting DTACK* or BERR*. Figure 6-1 illustrates that a master device
initiates a transfer on the VMEbus, which is converted into a MXIbus transfer, then back into a
VMEbus transfer to reach the target slave.
VXI-MXI
VXI-MXI
VXIbus
Mainframe
VXIbus
Mainframe
MXIbus
VMEbus VMEbus
Master
Slave
Figure 6-1. Master to Slave VMEbus/MXIbus Transfers
The VMEbus address lines map directly to the MXIbus address lines. The VMEbus requires six
address modifier lines, while MXIbus only defines five. The VMEbus address modifier lines
map to the MXIbus address modifier lines as shown in Table 6-2. The VXI-MXI responds to the
VMEbus address modifier codes shown in Table 6-3.
Table 6-2. VMEbus to MXIbus Address Modifier Line Map
VMEbus Address MXIbus Address
Modifier Line Modifier Line
VMEbus AM5 MXIbus AM4
VMEbus AM4 MXIbus AM3
VMEbus AM2 MXIbus AM2
VMEbus AM1 MXIbus AM1
VMEbus AM0 MXIbus AM0