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Chapter 4 Register Descriptions
© National Instruments Corporation 4-35 VXI-MXI User Manual
4r MXACFAILINT MXIbus ACFAIL Status Bit
When this bit is set, the VXIbus ACFAIL line is active and is
being driven across the MXIbus IRQ line. When this bit is cleared,
the ACFAIL signal is not driving the MXIbus IRQ line. This bit is
cleared on a hard reset.
4w MXACFAILEN MXIbus ACFAIL Enable Bit
Setting this bit enables the VXIbus ACFAIL line to be driven
across the MXIbus IRQ line. When this bit is cleared, the VXIbus
ACFAIL line is not mapped to the MXIbus IRQ line. This bit is
cleared on a hard reset.
3r/w LNGMXSCTO Long MXIbus System Controller Timeout Bit
When the VXI-MXI powers on, this bit is cleared and, if the
VXI-MXI is the MXIbus System Controller, the MXIbus System
Controller timeout is between 100 µs and 400 µs (selected by
jumper W8). When this bit is set, a longer MXIbus System
Controller timeout value is used (a value between 100 ms and
400 ms) if the VXI-MXI is the MXIbus System Controller. This
bit is cleared on a hard reset.
2r MXBERR MXIbus Bus Error Bit
If this bit is set, the VXI-MXI terminated the previous MXIbus
transfer by driving the MXIbus BERR line. This bit is cleared on
hard and soft reset and on successful MXIbus transfers.
2w BOFFCLR Backoff Condition Clear Bit
Setting this bit clears the BACKOFF bit in the Interrupt Status
Register. The BACKOFF condition occurs when a VMEbus
transfer to the MXIbus could not complete because another
MXIbus transfer directed to the VXI-MXI was already in progress.
This condition is called deadlock.
1r MXSYSFINT MXIbus SYSFAIL Status Bit
When this bit is set, the VXIbus SYSFAIL line is active and is
being driven across the MXIbus IRQ line. The VXIbus SYSFAIL
line is enabled to drive the MXIbus IRQ line with the SYSFOUT
bit in the MXIbus IRQ Configuration Register. When this bit is
cleared, the SYSFAIL signal is not driving the MXIbus IRQ line.
This bit is cleared on a hard reset.
0r PARERR Parity Error Bit
If this bit is set, a MXIbus parity error occurred on either the
address or the data portion of the last MXIbus transfer. This bit is
cleared on hard and soft resets and on MXIbus transfers without a
parity error.