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VXI-MXI User Manual Index-8 © National Instruments Corporation
SUBCLASS bit, 4-30
Subclass Register, 4-30
switches. See jumpers and switches.
Synchronous protocol, 6-3
SYSFAIL bit, 4-46
SYSFAIL signal, 2-5, 6-3
SYSFAILIE bit, 4-46
SYSFAILIN bit, 4-29
SYSFAILINT bit, 4-47
SYSFAILOUT bit, 4-29
SYSFIN bit, 4-37
SYSFOUT bit, 4-37
SYSRESET signal, 2-5, 6-3
SYSRSTIN bit, 4-29
SYSRSTOUT bit, 4-29
System Controller. See MXIbus System
Controller; VMEbus System Controller.
system logical address map configuration.
See logical address map configuration.
system power cycling requirements, 3-30
to 3-31
T
TERMPWR connection, 3-24
theory of operation
A16, A24, A32, and LA windows, 6-6
ACFAIL signal, 6-3
CLK10 circuitry, 6-2 to 6-3
ECL trigger lines, 6-2 to 6-3
functional description, 2-5 to 2-9
interrupt circuitry, 6-3 to 6-6
MXIbus
address/data and address modifier
transceivers, 6-11 to 6-12
control signal transceivers, 6-12
master mode state machine, 6-6
to 6-10
requester and arbiter circuitry, 6-12
to 6-14
slave mode state machine, 6-10
to 6-11
System Controller functions, 6-12
parity check and generation, 6-6
SYSFAIL signal, 6-3
SYSRESET signal, 6-3
TTL trigger lines, 6-2 to 6-3
VMEbus
address and address modifier
transceivers, 6-1
control signal transceivers, 6-2
data transceivers, 6-1
requester and arbiter circuitry, 6-2
VXI-MXI configuration registers, 6-6
VXIbus System Controller functions, 6-1
timing specifications, A-3
transceivers. See MXIbus transceivers;
VMEbus transceivers.
TRG IN connector, 6-2
TRG OUT connector, 6-2
TRIG[7-0]DIR bit, 4-49
TRIG[7-0]EN bit, 4-49
Trigger Asynchronous Acknowledge
Register, 4-50
Trigger Asynchronous interrupt
condition, 6-4
trigger control, INTX daughter card, 2-9
trigger input SMB termination, 3-22
trigger input termination, configuration, 3-22
Trigger Mode Selection Register, 4-41
to 4-44, 6-2
Trigger Synchronous Acknowledge
Register, 4-50
Trigger Synchronous interrupt condition, 6-4
TRIGIN bit, 4-43
TRIGINT bit, 4-46
TRIGINTIE bit, 4-46
TRIGOUT bit, 4-44
TTL trigger lines, 2-5, 6-2 to 6-3
Two-Frame VXI System, E-1
U
unpacking the VXI-MXI interface
module, 1-7
V
VERSION bit, 4-8
VME BTO chain position, configuration,
3-10 to 3-12
VME BTO circuitry
configuration, 3-8 to 3-9
interlocked arbitration mode timing, 3-13
jumpers and switches, 3-9
VMEbus
A16 register resource configuration, 3-31
capability codes, A-1
compliance levels, 2-3 to 2-4
modules, 2-2 to 2-3
request level configuration, 3-7 to 3-8
requester and arbiter circuitry, 2-5, 6-2