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Register Descriptions Chapter 4
VXI-MXI User Manual 4-32 © National Instruments Corporation
MXI Address
Modifiers
RMWMODE
Bit
Routing
Block X MXIbus block to VMEbus block
Non-Block 0
MXIbus RMW cycle to VMEbus
RMW cycle
1 MXIbus block to VMEbus single
cycle
14r/w CMODE Comparison Mode Bit
This bit selects the range comparison mode for the logical address,
A16, A24, and A32 Window Mapping Registers. If CMODE is
cleared, a Base/Size range comparison is used to determine the
range of addresses in the windows. If CMODE is set, an upper and
lower bound is used to determine the range of addresses in the
windows. This bit is cleared on hard and soft resets.
13-12r, 1 Reserved Bits
7w,
1-0w These bits are reserved and read back as ones. Write a zero when
writing to these bits.
13w ECL1EN ECL Trigger 1 Enable Bit
Setting this bit enables the ECL Trigger line 1 to be mapped to the
Trigger Out SMB connector or from the Trigger In SMB connector
on the front panel, as specified by the ECL1DIR bit. Clearing this
bit disables the mapping of ECL Trigger Line 1 to the front panel
SMB connectors. This bit is cleared on a hard reset.
12w ECL1DIR ECL Trigger Line 1 Direction Bit
If the ECL1EN bit is clear, this bit has no meaning. If ECL1EN is
set, this bit controls the routing of ECL trigger line 1.
If this bit is set, ECL trigger line 1 is driven by the signal received
on the front panel Trigger In SMB connector. If this bit is clear,
ECL trigger line 1 is driven out of the mainframe through the
Trigger Out SMB on the front panel. This bit is cleared on a hard
reset.
ECLxEN ECLxDIR Routing
0 X Disabled
10
ECL Trigger Line X drives TRIG
OUT SMB
1 TRIG IN SMB drives ECL
Trigger Line X