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© National Instruments Corporation Index-3 VXI-MXI User Manual
BTO. See VME BTO chain position; VME
BTO circuitry.
bus master compliance levels, 2-4
bus slave compliance levels, 2-3
C
cable connections
INTX daughter card, 3-27
MXIbus, 3-28 to 3-30
capability codes
MXIbus, A-2
VMEbus, A-1
VXIbus, A-1
CLK10 circuitry
definition, 2-5
INTX daughter card, 2-9
theory of operation, 6-2 to 6-3
CLK10 source configuration, 3-18 to 3-22
damage warning, 3-22
EXT CLK SMB input/output, 3-20
INTX CLK10 mapping, 3-20 to 3-22
CMODE bit
A16 Window Map Register, 4-14, 4-16
A24 Window Map Register, 4-18, 4-20
A32 Window Map Register, 4-22, 4-24
description, 4-32
Logical Address Window Register,
4-10, 4-12
compliance levels, VMEbus, 2-3 to 2-4
configuration. See also installation; logical
address map configuration; multiframe RM
operation.
A16 register resources, 3-31
CLK10 source, 3-18 to 3-22
EXT CLK SMB input/output, 3-20
INTX CLK10 mapping, 3-20 to 3-22
factory default settings for VXI-MXI
with INTX, 3-3
without INTX, 3-2
interlocked arbitration mode, 3-13 to 3-14
logical address, 3-6 to 3-7
MXIbus fairness option, 3-17
MXIbus System Controller, 3-14 to 3-15
MXIbus System Controller timeout, 3-16
parts locator diagram
VXI-MXI, C-2
VXI-MXI with INTX, 3-3
VXI-MXI without INTX, 3-2
removing metal enclosure, 3-4
reset signal selection, 3-23
Slot 0 settings, 3-4 to 3-5
trigger input termination, 3-22
two-frame system, E-1
VMEbus devices in VXIbus/MXIbus
systems, 3-31
VMEbus request level, 3-7 to 3-8
VMEbus timeout chain position, 3-10
to 3-12
VMEbus timeout value, 3-8 to 3-9
connector descriptions
INTX connector, D-3 to D-4
MXIbus connector, D-1 to D-2
customer communication, xii, F-1
D
daughter card. See INTX daughter card.
deadlock conditions
causes, 3-13
interlocked arbitration mode, 3-13
interrupt circuitry, 6-3
MXIbus master mode state machine, 6-10
DEVCLASS bit, 4-4
Device Type Register, 4-6
DIRQ[7-1] bit, 4-47
documentation
organization, xi
related documentation, xii
Drive Triggers/Read LA Register, 4-39
to 4-40, 6-2
DRVECL0 bit, 4-40
DRVECL1 bit, 4-40
DSYSFAIL bit, 4-33
DSYSRST bit, 4-34
DTACK signal, 3-8, 3-16
DTB arbiter compliance level (PRI), 2-3
DTB requester compliance level (ROR), 2-3
DTRIG[7-0] bit, 4-39
E
ECL trigger lines, 2-5, 6-2 to 6-3
ECL0DIR bit, 4-33
ECL0EN bit, 4-33
ECL1DIR bit, 4-32
ECL1EN bit, 4-32
ECLSTAT0 bit, 4-43
ECLSTAT1 bit, 4-43
EDTYPE bit, 4-7
EINT[7-1]DIR bit, 4-26
EINT[7-1]EN bit, 4-26
electrical specifications, A-2