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Chapter 6 Theory of Operation
© National Instruments Corporation 6-3 VXI-MXI User Manual
The Synchronous protocol is a single trigger line broadcast that does not require an acknowledge
from its acceptors. The source must assert the trigger for a minimum of 30 ns and allow at least
50 ns between assertions. The rising edge or falling edge can be specified to initiate action in the
receiver.
The Semi-synchronous protocol uses a single trigger line to communicate between a single
source and multiple acceptors. The source device initiates the protocol by pulsing the trigger line
for a minimum of 50 ns. The acceptors must then assert the same trigger line within 40 ns and
release the line when each is ready for the next operation. The source sees the trigger line
unasserted when all acceptors have released the trigger line, indicating that the operation is
complete. The Trigger Mode Selection Register can be used to configure the VXI-MXI to source
and receive the semi-synchronous protocol.
The Semi-synchronous protocol must be separated into two trigger lines when extended between
two VXIbus mainframes: one line for the source and one line for the acceptor. Because acceptor
devices must assert the trigger line within 40 ns in response to the source asserting the line, this
protocol can only be used for short extensions.
The Start/Stop protocol is used to start and stop modules synchronously on the same 10 MHz
clock. The Slot 0 device drives the selected trigger line and synchronizes it to the 10 MHz clock.
When asserted, the trigger line indicates a Start signal. When unasserted, the trigger line
indicates a Stop signal.
The VXI-MXI can be configured either to drive its 10 MHz VXIbus CLK10 signal to other
mainframes or to receive a 10 MHz CLK10 signal from another mainframe via the EXT CLK
SMB connector on the front panel. Multiple mainframes can be synchronized if configured to
operate with the same 10 MHz CLK10 system clock.
SYSFAIL, ACFAIL, and SYSRESET
The VMEbus signals SYSFAIL*, ACFAIL*, and SYSRESET* can be individually monitored
and driven by the VXI-MXI card. These three signals can also be used individually to generate
an interrupt across the MXIbus IRQ line and/or one of the VMEbus interrupt request lines.
Interrupt Circuitry
The MXIbus has one interrupt line, IRQ. This IRQ line can be mapped to or driven by any of the
VMEbus interrupt lines IRQ[7–1]* or driven by VMEbus signals SYSFAIL*, ACFAIL*, and/or
SYSRESET*, or the TRIGINT trigger interrupt. Registers in the MXIbus configuration space
are used to configure the MXIbus IRQ* line operation.
Five local VXI-MXI conditions can be enabled to drive the VMEbus interrupt lines: SYSFAIL*
asserted, ACFAIL* asserted, the Backoff condition, a Trigger Synchronous interrupt condition,
and a Trigger Asynchronous interrupt condition.
The Backoff condition occurs when the VXI-MXI is a MXIbus master arbitrating for the
MXIbus and a MXIbus transfer requesting the VMEbus is received. This situation results in a
deadlock condition. The MXIbus master circuitry must send a BERR* to the VMEbus master
initiating the MXIbus transfer so that the incoming MXIbus transfer can complete. The VMEbus
master can monitor the backoff interrupt. If the interrupt occurs, the master should retry its last
MXIbus operation because it did not complete due to the deadlock condition.