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Chapter 6 Theory of Operation
© National Instruments Corporation 6-9 VXI-MXI User Manual
Table 6-4. VMEbus/MXIbus Transfer Size Comparison
VMEbus MXIbus Byte Locations
DS1* DS0* A01 LWORD* Size AD01 AD00 D24-31 D16-23 D08-15 D00-07
8-bit Transfers
Byte(0) 0101000 Byte(0)
Byte(1) 1001001 Byte(1)
Byte(2) 0111010 Byte(2)
Byte(3) 1011011 Byte(3)
16-bit Transfers
Byte(0-1) 0001100 Byte(0) Byte(1)
Byte(2-3) 0011110 Byte(2) Byte(3)
32-bit Transfers
Byte(0-3) 0000111Byte(0) Byte(1) Byte(2) Byte(3)
The VXI-MXI generates and checks the parity of the address and data portions of all MXIbus
cycles. The MXIbus PAR* signal is generated and sent during the address portion of all MXIbus
cycles initiated by the VXI-MXI. It is also generated and sent during the data portion of MXIbus
master write cycles. When the VXI-MXI detects a parity error in the data transfer portion of a
MXIbus read cycle, it asserts the VMEbus BERR* signal to indicate to the VMEbus host that the
data read contains an error.
Deadlock occurs when a VMEbus master is arbitrating for the MXIbus at the same time that a
remote MXIbus device is requesting the same VMEbus. This situation is shown in Figure 6-2
where the VMEbus master arbitrating for the MXIbus is the VXI-MXI in VXIbus Mainframe #2
and the remote MXIbus device requesting the VMEbus is in VXIbus Mainframe #1.
To overcome the deadlock condition, the VMEbus master that is arbitrating for the MXIbus
terminates the transfer request by sending a BERR* to the VMEbus. The remote MXIbus
transfer to the VMEbus can then arbitrate for the VMEbus and complete the transfer. In the
situation in Figure 6-2, the VXI-MXI in VXIbus Mainframe #2 will send the VMEbus BERR*
signal to resolve the deadlock condition. A Backoff condition occurs when a MXIbus master
must terminate a transfer before acquiring the MXIbus in order to prevent deadlock. A VMEbus
interrupt can be generated on this condition.