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© National Instruments Corporation Index-5 VXI-MXI User Manual
J
jumpers and switches
CLK10 source signal options, 3-19
EXT CLK SMB input/output, 3-20
factory default settings
VXI-MXI with INTX, 3-3
VXI-MXI without INTX, 3-2
interlocked arbitration mode, 3-14
INTX CLK10 mapping switches, 3-21
to 3-22
logical address, 3-6 to 3-7
MXIbus fairness option, 3-17
MXIbus System Controller, 3-15
MXIbus System Controller timeout, 3-16
non-Slot 0 selection, 3-5
reset signal settings, 3-23
Slot 0 settings, 3-4
trigger input termination, 3-22
VME BTO chain position, 3-10 to 3-12
VME BTO value selection, 3-9
VMEbus request level, 3-8
L
LABASE[7-0] bits, 4-11
LADD[7-0] bit, 4-39
LADIR bit, 4-10, 4-11
LAEN bit, 4-10, 4-11
LAHIGH[7-0] bits, 4-12
LALOW[7-0] bits, 4-12
LASIZE[2-0] bits, 4-11
LINT[3-1] bits, 4-45
LNGMXSCTO bit, 3-16, 4-35
LOCKED bit, 4-36
logical address
configuration, 3-6 to 3-7
definition, 3-6
logical address map configuration, 5-1
to 5-34
A16 address map
blank worksheets, 5-29 to 5-34
examples, 5-25
planning, 5-21 to 5-24
worksheet examples, 5-26 to 5-28
Base/Size configuration format, 5-3
to 5-4
basic configurations (illustration), 5-2
examples, 5-8 to 5-9
high/low configuration format, 5-5
multiframe RM operation, 5-35 to 5-38
A24 and A32 addressing
windows, 5-38
example, 5-36 to 5-38
steps for planning, 5-35 to 5-36
overview, 5-1
planning, 5-1 to 5-3
procedure, 5-5 to 5-7
worksheets
alternative worksheets, 5-18 to 5-21
blank worksheets, 5-13 to 5-17
examples, 5-10 to 5-12
Logical Address Window Register, 4-10
to 4-13
bit descriptions, 4-10 to 4-11, 4-12
definition, 2-7
description, 4-10
example, 4-11
format
CMODE bit cleared, 4-10
CMODE bit set, 4-12
theory of operation, 6-6
Low configuration format, 5-5
M
MANID bit, 4-5
master mode state machine. See MXIbus
master mode state machine.
metal enclosure for VXI-MXI, removing,
3-4, C-1
MIRQ[7-1]DIR bit, 4-37 to 4-38
MIRQ[7-1]EN bit, 4-37, 4-38
mnemonics key, B-1 to B6
MODEL bit, 4-6
MODID* bit, 4-7
MODID Register, 4-9
MODID[12-0] bits, 4-9
multiframe RM
PC configuration, 5-2
VXIbus mainframe configuration, 5-2
multiframe RM operation
A24 and A32 addressing window
configuration, 5-38
logical address window configuration,
5-35 to 5-38
system administration and initiation, 5-39
MXACFAILEN bit, 4-35
MXACFAILINT bit, 4-35
MXBERR bit, 4-35
MXIbus
cable connections, 3-28 to 3-30
capability codes, A-2