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Register Descriptions Chapter 4
VXI-MXI User Manual 4-40 © National Instruments Corporation
1w DRVECL1 Drive ECL Trigger Line 1 Bit
Setting this bit asserts the VXIbus ECL Trigger Line 1 after
synchronizing the signal with the 10 MHz clock.
0w DRVECL0 Drive ECL Trigger Line 0
Setting this bit asserts the VXIbus ECL Trigger Line 0 after
synchronizing the signal with the 10 MHz clock.