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Register Descriptions Chapter 4
VXI-MXI User Manual 4-34 © National Instruments Corporation
8r FAIR VXI-MXI Fairness Status Bit
When this bit is set, the VXI-MXI is configured as a fair MXIbus
requester. If this bit is cleared, the VXI-MXI is configured as an
unfair MXIbus requester. FAIR is selected with slide switch S2.
This bit is not affected by hard or soft resets.
8w DSYSRST Drive SYSRESET line Bit
Setting this bit will cause the VXIbus SYSRESET line to pulse
asserted for a minimum of 200 ms. This bit is automatically
cleared after the assertion of SYSRESET.
7r MXISC MXIbus System Controller Status Bit
When this bit is set, the VXI-MXI is configured as the MXIbus
System Controller. When this bit is cleared, the VXI-MXI is not
configured as the MXIbus System Controller. MXISC is selected
with slide switch S4. This bit is not affected by hard or soft resets.
6r MXTRIGINT MXIbus Trigger Interrupt Status Bit
When this bit is set, the VXIbus Trigger Interrupt signal (TRIGINT
in the Interrupt Status Register) is active and is being driven across
the MXIbus IRQ line. When this bit is cleared, the TRIGINT
signal is not driving the MXIbus IRQ line. This bit is cleared on a
hard reset.
6w MXTRIGEN MXIbus Trigger Interrupt Enable Bit
Setting this bit enables the VXIbus Trigger Interrupt signal
(TRIGINT in the Interrupt Status Register) to be driven across the
MXIbus IRQ line. When this bit is cleared, the TRIGINT signal is
not mapped to the MXIbus IRQ line. This bit is cleared on a hard
reset.
5r MXSRSTINT MXIbus SYSRESET Status Bit
When this bit is set, the VXIbus SYSRESET line is active and is
being driven across the MXIbus IRQ line. When this bit is cleared,
the SYSRESET signal is not driving the MXIbus IRQ line. This
bit is cleared on a hard reset.
5w MXSRSTEN MXIbus SYSRESET Enable Bit
Setting this bit enables the VXIbus SYSRESET line to be driven
across the MXIbus IRQ line. When this bit is cleared, the VXIbus
SYSRESET line is not mapped to the MXIbus IRQ line. This bit
is cleared on a hard reset.