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DS610 July 16, 2007 www.xilinx.com 1
Product Specification
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
Module 1:
Introduction and Ordering Information
DS610-1 (v2.0) July 16, 2007
• Introduction
• Features
• Architectural Overview
• Configuration Overview
• General I/O Capabilities
• Supported Packages and Package Marking
• Ordering Information
Module 2:
Functional Description
DS610-2 (v2.0) July 16, 2007
The functionality of the Spartan™-3A DSP FPGA family is
described in the following documents.
• UG331:
Spartan-3 Generation FPGA User Guide
- Clocking Resources
- Digital Clock Managers (DCMs)
-Block RAM
- Configurable Logic Blocks (CLBs)
· Distributed RAM
· SRL16 Shift Registers
· Carry and Arithmetic Logic
-I/O Resources
- Programmable Interconnect
-ISE
TM
Software Design Tools and IP Cores
- Embedded Processing and Control Solutions
- Pin Types and Package Overview
- Package Drawings
- Powering FPGAs
- Power Management
• UG431
:
XtremeDSP™ DSP48A for Spartan-3A DSP FPGAs
User Guide
- DSP48A Slice Design Considerations
- DSP48A Architecture Highlights
· 18 x 18-Bit Multipliers
· 48-Bit Accumulator
· 18-bit Pre-Adder
- DSP48A Application Examples
• UG332
:
Spartan-3 Generation Configuration User Guide
- Configuration Overview
- Configuration Pins and Behavior
- Bitstream Sizes
- Detailed Descriptions by Mode
· Master Serial Mode using Platform Flash PROM
· Master SPI Mode using Commodity Serial Flash
· Master BPI Mode using Commodity Parallel Flash
· Slave Parallel (SelectMAP) using a Processor
· Slave Serial using a Processor
· JTAG Mode
- ISE iMPACT Programming Examples
- MultiBoot Reconfiguration
- Design Authentication using Device DNA
Module 3:
DC and Switching Characteristics
DS610-3 (v2.0) July 16, 2007
• DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
• Switching Characteristics
- I/O Timing
- Configurable Logic Block (CLB) Timing
- Digital Clock Manager (DCM) Timing
-Block RAM Timing
- XtremeDSP Slice Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS610-4 (v2.0) July 16, 2007
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
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Spartan-3A DSP FPGA Family:
Data Sheet
DS610 July 16, 2007
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Product Specification
R
SPARTAN-3A DSP
SPARTAN-3A DSP
www.xilinx.com/spartan3adsp