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DS610-2 (v2.0) July 16, 2007 www.xilinx.com 9
Product Specification
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
Introduction
The functionality of the Spartan™-3A DSP FPGA family is
described in the following documents. The topics covered in
each guide are listed below.
• UG431
:
XtremeDSP DSP48A for Spartan-3A DSP
FPGAs User Guide
♦ XtremeDSP DSP48A Slices
♦ XtremeDSP DSP48A Pre-Adder
• UG331
:
Spartan-3 Generation FPGA User Guide
♦ Clocking Resources
♦ Digital Clock Managers (DCMs)
♦ Block RAM
♦ Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
♦ I/O Resources
♦ Programmable Interconnect
♦ ISE™ Software Design Tools
♦ IP Cores
♦ Embedded Processing and Control Solutions
♦ Pin Types and Package Overview
♦ Package Drawings
♦ Powering FPGAs
♦ Power Management
• UG332
:
Spartan-3 Generation Configuration User
Guide
♦ Configuration Overview
- Configuration Pins and Behavior
- Bitstream Sizes
♦ Detailed Descriptions by Mode
- Master Serial Mode using Xilinx Platform Flash
PROM
- Master SPI Mode using Commodity SPI Serial
Flash PROM
- Master BPI Mode using Commodity Parallel
NOR Flash PROM
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
♦ ISE iMPACT Programming Examples
♦ MultiBoot Reconfiguration
♦ Design Authentication using Device DNA
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Revision History
The following table shows the revision history for this document.
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Spartan-3A DSP FPGA Family:
Functional Description
DS610-2 (v2.0) July 16, 2007
0
Product Specification
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Date Version Revision
04/02/07 1.0 Initial Xilinx release.
05/25/07 1.0.1 Minor edits.
06/18/07 1.2 Updated for Production release.
07/16/07 2.0 Added Low-power options; no changes to this module.