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DC and Switching Characteristics
DS610-3 (v2.0) July 16, 2007 www.xilinx.com 41
Product Specification
R
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
DLL tables (Ta bl e 35 and Ta ble 36) apply to any application
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
(Table 37 through Table 40) supersede any corresponding
ones in the DLL tables. DLL specifications that do not
change with the addition of DFS or PS functions are
presented in Ta ble 35 and Table 36 .
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Delay-Locked Loop (DLL)
Table 35:
Recommended Operating Conditions for the DLL
Symbol Description
Speed Grade
Units
-5 -4
Min Max Min Max
Input Frequency Ranges
F
CLKIN
CLKIN_FREQ_DLL Frequency of the CLKIN clock input 5
(2)
280
(3)
5
(2)
250
(3)
MHz
Input Pulse Requirements
CLKIN_PULSE CLKIN pulse width as a
percentage of the CLKIN
period
F
CLKIN
< 150 MHz 40% 60% 40% 60% -
F
CLKIN
> 150 MHz 45% 55% 45% 55% -
Input Clock Jitter Tolerance and Delay Path Variation
(4)
CLKIN_CYC_JITT_DLL_LF Cycle-to-cycle jitter at the
CLKIN input
F
CLKIN
< 150 MHz - ±300 -±300ps
CLKIN_CYC_JITT_DLL_HF F
CLKIN
> 150 MHz - ±150 -±150ps
CLKIN_PER_JITT_DLL Period jitter at the CLKIN input
-±1-±1ns
CLKFB_DELAY_VAR_EXT Allowable variation of off-chip feedback delay from
the DCM output to the CLKFB input
-±1-±1ns
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 37.
3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock period by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
5. The DCM specifications are guaranteed when both adjacent DCMs are locked