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DC and Switching Characteristics
DS610-3 (v2.0) July 16, 2007 www.xilinx.com 27
Product Specification
R
Table 22:
Timing for the IOB Output Path
Symbol Description Conditions Device
Speed Grade
Units
-5 -4
Max Max
Clock-to-Output Times
T
IOCKP
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin
LVCMOS25
(2)
, 12 mA output
drive, Fast slew rate
All 2.87 3.13 ns
Propagation Times
T
IOOP
The time it takes for data to travel from
the IOB’s O input to the Output pin
LVCMOS25
(2)
, 12 mA output
drive, Fast slew rate
All 2.78 2.91 ns
T
IOOLP
The time it takes for data to travel from
the O input through the OFF latch to
the Output pin
2.70 2.85 ns
Set/Reset Times
T
IOSRP
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
LVCMOS25
(2)
, 12 mA output
drive, Fast slew rate
All 3.63 3.89 ns
T
IOGSRQ
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
8.62 9.65 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in
Table 7 and Table 10.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true,
add
the appropriate Output adjustment from Table 24.
Table 23:
Timing for the IOB Three-State Path
Symbol Description Conditions Device
Speed Grade
Units
-5 -4
Max Max
Synchronous Output Enable/Disable Times
T
IOCKHZ
Time from the active transition at the OTCLK
input of the Three-state Flip-Flop (TFF) to when
the Output pin enters the high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All 1.13 1.39 ns
T
IOCKON
(2)
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
All 3.08 3.35 ns
Asynchronous Output Enable/Disable Times
T
GTS
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All 9.47 10.36 ns
Set/Reset Times
T
IOSRHZ
Time from asserting TFF’s SR input to when
the Output pin enters a high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All 1.61 1.86 ns
T
IOSRON
(2)
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
All 3.57 3.82 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in
Table 7 and Table 10.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true,
add
the appropriate Output adjustment from Table 24.