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Pinout Descriptions
DS610-4 (v2.0) July 16, 2007 www.xilinx.com 97
Product Specification
R
Revision History
The following table shows the revision history for this document.
www.xilinx.com/spartan3adsp
Date Version Revision
04/02/07 1.0 Initial Xilinx release.
05/25/07 1.1 Updates to Table 58, Table 60, Table 61, Table 62, Table 63, Table 64, Table 65, Table 66. Corrected
VREF pins in XC3S1800A FG676 (Table 67). Updated FG676 package footprints for XC3SD1800A
FPGA (Figure 17) and XC3SD3400A FPGA (Figure 18). Minor edits.
06/18/07 1.2 Updated for Production release.
07/16/07 2.0 Added Low-power options.. Added advance thermal data to Table 59.
SPARTAN-3A DSP
SPARTAN-3A DSP