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Chapter 8 Integer Optimizations 165
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
by 6: lea
reg1
, [
reg1
+
reg1
*2] ; 3 cycles
add
reg1
,
reg1
by 7: mov
reg2
,
reg1
; 2 cycles
shl
reg1
, 3
sub
reg1
,
reg2
by 8: shl
reg1
, 3 ; 1 cycle
by 9: lea
reg1
, [
reg1
+
reg1
*8] ; 2 cycles
by 10: lea
reg1
, [
reg1
+
reg1
*4] ; 3 cycles
add
reg1
,
reg1
by 11: lea
reg2
, [
reg1
+
reg1
*8] ; 3 cycles
add
reg1
,
reg1
add
reg1
,
reg2
by 12: lea
reg1
, [
reg1
+
reg1
*2] ; 3 cycles
shl
reg1
, 2
by 13: lea
reg2
, [
reg1
+
reg1
*2] ; 3 cycles
shl
reg1
, 4
sub
reg1
,
reg2
by 14: lea
reg2
, [
reg1
+
reg1
] ; 3 cycles
shl
reg1
, 4
sub
reg1
,
reg2
by 15: mov
reg2
,
reg1
; 3 cycles
shl
reg1
, 4
sub
reg1
,
reg2
by 16: shl
reg1
, 4 ; 1 cycle
by 17: mov
reg2
,
reg1
; 2 cycles
shl
reg1
, 4
add
reg1
,
reg2
by 18: lea
reg1
, [
reg1
+
reg1
*8] ; 3 cycles
add
reg1
,
reg1
by 19: lea
reg2
, [
reg1
+
reg1
*2] ; 3 cycles
shl
reg1
, 4
add
reg1
,
reg2
by 20: lea
reg1
, [
reg1
+
reg1
*4] ; 3 cycles
shl
reg1
, 2
by 21: lea
reg2
, [
reg1
+
reg1
*4] ; 3 cycles
shl
reg1
, 4