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280 Instruction Latencies Appendix C
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
CMP mreg16/32/64, imm8 (sign extended) 83h 11-111-xxx DirectPath 1
CMPS mem8, mem8 A6h VectorPath 6 6
CMPS mem16/32/64, mem16/32/64 A7h VectorPath 6 6
CMPSB A6h VectorPath 6 6
CMPSD A7h VectorPath 6 6
CMPSQ A7 VectorPath 6 7
CMPSW A7h VectorPath 6 6
CMPXCHG mem8, reg8 0Fh B0h mm-xxx-xxx VectorPath 5
CMPXCHG mreg8, reg8 0Fh B0h 11-xxx-xxx VectorPath 3
CMPXCHG mem16/32/64, reg16/32/64 0Fh B1h mm-xxx-xxx VectorPath 5
CMPXCHG mreg16/32/64, reg16/32/64 0Fh B1h 11-xxx-xxx VectorPath 3
CMPXCHG8B mem64 0Fh C7h mm-xxx-xxx VectorPath 10
CMPXCHG16B mem128 0Fh C7h mm-xxx-xxx VectorPath
CPUID (function 0) 0Fh A2h VectorPath 36
CPUID (function 1) 0Fh A2h VectorPath 152
CPUID (function 2) 0Fh A2h VectorPath 38
CPUID (function 8000_0001h) 0Fh A2h VectorPath
CPUID (function 8000_0002h) 0Fh A2h VectorPath
CPUID (function 8000_0003h) 0Fh A2h VectorPath
CPUID (function 8000_0004h) 0Fh A2h VectorPath
CPUID (function 8000_0007h) 0Fh A2h VectorPath
CPUID (function 8000_0008h) 0Fh A2h VectorPath
CWD/CDQ/CQO 99h DirectPath 1
DAA 27h VectorPath 7
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.