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Chapter 4 Instruction-Decoding Optimizations 79
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
Example
These two instructions can be replaced by one instruction.
movl 0x4c65a,%r11
movl (%r11,%r8,8),%r11
becomes:
movl 0x4c65a(,%r8,8),%r11
Number of Bytes Latency Instruction
84 cmpb %al,
0x68e35(%r10,%r13)