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Appendix C Instruction Latencies 301
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
VERW mem16 0Fh 00h mm-101-xxx VectorPath 11
WAIT 9Bh DirectPath ~0 5
WBINVD 0Fh 09h VectorPath 9796/
9474
7
WRMSR 0Fh 30h VectorPath 134
XADD mreg8, reg8 0Fh C0h 11-100-xxx VectorPath 2
XADD mem8, reg8 0Fh C0h mm-100-xxx VectorPath 5
XADD mreg16/32/64, reg16/32/64 0Fh C1h 11-101-xxx VectorPath 2
XADD mem16/32/64, reg16/32/64 0Fh C1h mm-101-xxx VectorPath 5
XCHG reg8, mreg8 86h 11-xxx-xxx VectorPath 2
XCHG mreg8, reg8 86h 11-xxx-xxx VectorPath 2
XCHG reg8, mem8 86h mm-xxx-xxx VectorPath 16
XCHG mem8, reg8 86h mm-xxx-xxx VectorPath 16
XCHG reg16/32/64, mreg16/32/64 87h 11-xxx-xxx VectorPath 2
XCHG mreg16/32/64, reg16/32/64 87h 11-xxx-xxx VectorPath 2
XCHG reg16/32/64, mem16/32/64 87h mm-xxx-xxx VectorPath 16
XCHG mem16/32/64, reg16/32/64 87h mm-xxx-xxx VectorPath 16
XCHG AX/EAX/RAX, AX/EAX/RAX/(R8)
(NOP)
90h DirectPath ~0 5
XCHG AX/EAX/RAX, CX/ECX/RCX/(R9) 91h VectorPath 2
XCHG AX/EAX/RAX, DX/EDX/RDX/(R10) 92h VectorPath 2
XCHG AX/EAX/RAX, BX/EBX/RBX/(R11) 93h VectorPath 2
XCHG AX/EAX/RAX, SP/ESP/RSP/(R12) 94h VectorPath 2
XCHG AX/EAX/RAX, BP/EBP/RBP/(R13) 95h VectorPath 2
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.