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Appendix C Instruction Latencies 291
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
POP FS 0Fh A1h VectorPath 10
POP GS 0Fh A9h VectorPath 10
POP AX/EAX/RAX/(R8) 58h Double 3
POP CX/ECX/RCX/(R9) 59h Double 3
POP DX/EDX/RDX/(R10) 5Ah Double 3
POP BX/EBX/RBX/(R11) 5Bh Double 3
POP SP/ESP/RSP/(R12) 5Ch Double 3
POP BP/EBP/RBP/(R13) 5Dh Double 3
POP SI/ESI/RSI/(R14) 5Eh Double 3
POP DI/EDI/RDI/(R15) 5Fh Double 3
POP mreg 16/32/64 8Fh 11-000-xxx VectorPath 3
POP mem 16/32/64 8Fh mm-000-xxx VectorPath 3
POPA/POPAD 61h VectorPath 6
POPF/POPFD/POPFQ 9Dh VectorPath 15
PUSH ES 06h VectorPath 3 2
PUSH CS 0Eh VectorPath 3
PUSH FS 0Fh A0h VectorPath 3
PUSH GS 0Fh A8h VectorPath 3
PUSH SS 16h VectorPath 3
PUSH DS 1Eh VectorPath 3 2
PUSH AX/EAX/RAX/(R8) 50h DirectPath 3 2
PUSH CX/ECX/RCX/(R9) 51h DirectPath 3 2
PUSH DX/EDX/RDX/(R10) 52h DirectPath 3 2
PUSH BX/EBX/RBX/(R11) 53h DirectPath 3 2
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.