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Appendix C Instruction Latencies 293
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
RCR mreg16/32/64, imm8 C1h 11-011-xxx VectorPath 5
RCR mem16/32/64, imm8 C1h mm-011-xxx VectorPath 6
RCR mreg8, 1 D0h 11-011-xxx DirectPath 1
RCR mem8, 1 D0h mm-011-xxx DirectPath 4
RCR mreg16/32/64, 1 D1h 11-011-xxx DirectPath 1
RCR mem16/32/64, 1 D1h mm-011-xxx DirectPath 4
RCR mreg8, CL D2h 11-011-xxx VectorPath 4
RCR mem8, CL D2h mm-011-xxx VectorPath 6
RCR mreg16/32/64, CL D3h 11-011-xxx VectorPath 4
RCR mem16/32/64, CL D3h mm-011-xxx VectorPath 6
RDMSR 0Fh 32h VectorPath 87
RDPMC 0Fh 33h VectorPath ~
RDTSC 0Fh 31h VectorPath 12
RET near imm16 C2h VectorPath 5
RET near C3h Double 5
RET far imm16 (no CPL change) CAh VectorPath 31–44
RET far imm16 (CPL change) CAh VectorPath 57-72
RET far (no CPL change) CBh VectorPath 31–44
RET far (CPL change) CBh VectorPath 57-72
ROL mreg8, imm8 C0h 11-000-xxx DirectPath 1 3
ROL mem8, imm8 C0h mm-000-xxx DirectPath 4 3
ROL mreg16/32/64, imm8 C1h 11-000-xxx DirectPath 1 3
ROL mem16/32/64, imm8 C1h mm-000-xxx DirectPath 4 3
ROL mreg8, 1 D0h 11-000-xxx DirectPath 1
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.