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256 Microarchitecture for AMD Athlon™ 64 and AMD Opteron™ Processors Appendix A
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
Table 11 provides specifications on the L1 data cache for various AMD processors.
A.11 Integer Scheduler
The integer scheduler is based on a three-wide queuing system (also known as a reservation station)
that feeds three integer execution positions or pipes. The reservation stations are eight entries deep,
for a total queuing system of 24 integer macro-ops. Each reservation station divides the macro-ops
into integer and address generation micro-ops, as required.
A.12 Integer Execution Unit
The integer execution pipeline consists of three identical pipes—0, 1, and 2. Each integer pipe
consists of an integer execution unit—or arithmetic-logic unit (ALU)—and an address generation unit
(AGU). The integer execution pipeline is organized to match the three macro-op dispatch pipes in the
ICU as shown in Figure 7.
Figure 7. Integer Execution Pipeline
Macro-ops are broken down into micro-ops in the schedulers. Micro-ops are executed when their
operands are available, either from the register file or result buses. Micro-ops from a single operation
Table 11. L1 Data Cache Specifications by Processor
Processor name Family Model Associativity Size (Kbytes)
AMD Athlon™ XP
Processor
662 ways 64
AMD Athlon™ 64
Processor
15 All 2 ways 64
AMD Opteron™
Processor
15 All 2 ways 64
ALU 0 AGU 0 ALU 1 AGU 1 ALU 2 AGU 2
Integer Multiplier
Instruction Control Unit
Scheduler 0
Macro-ops
(8 entries)
Scheduler 1
(8 entries)
Scheduler 2
(8 entries)
Micro-ops