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294 Instruction Latencies Appendix C
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
ROL mem8, 1 D0h mm-000-xxx DirectPath 4
ROL mreg16/32/64, 1 D1h 11-000-xxx DirectPath 1
ROL mem16/32/64, 1 D1h mm-000-xxx DirectPath 4
ROL mreg8, CL D2h 11-000-xxx DirectPath 1 3
ROL mem8, CL D2h mm-000-xxx DirectPath 4 3
ROL mreg16/32/64, CL D3h 11-000-xxx DirectPath 1 3
ROL mem16/32/64, CL D3h mm-000-xxx DirectPath 4 3
ROR mreg8, imm8 C0h 11-001-xxx DirectPath 1 3
ROR mem8, imm8 C0h mm-001-xxx DirectPath 4 3
ROR mreg16/32/64, imm8 C1h 11-001-xxx DirectPath 1 3
ROR mem16/32/64, imm8 C1h mm-001-xxx DirectPath 4 3
ROR mreg8, 1 D0h 11-001-xxx DirectPath 1
ROR mem8, 1 D0h mm-001-xxx DirectPath 4
ROR mreg16/32/64, 1 D1h 11-001-xxx DirectPath 1
ROR mem16/32/64, 1 D1h mm-001-xxx DirectPath 4
ROR mreg8, CL D2h 11-001-xxx DirectPath 1 3
ROR mem8, CL D2h mm-001-xxx DirectPath 4 3
ROR mreg16/32/64, CL D3h 11-001-xxx DirectPath 1 3
ROR mem16/32/64, CL D3h mm-001-xxx DirectPath 4 3
SAHF 9Eh DirectPath 1
SAR mreg8, imm8 C0h 11-111-xxx DirectPath 1 3
SAR mem8, imm8 C0h mm-111-xxx DirectPath 4 3
SAR mreg16/32/64, imm8 C1h 11-111-xxx DirectPath 1 3
SAR mem16/32/64, imm8 C1h mm-111-xxx DirectPath 4 3
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.