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302 Instruction Latencies Appendix C
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
XCHG AX/EAX/RAX, SI/ESI/RSI/(R14) 96h VectorPath 2
XCHG AX/EAX/RAX, DI/EDI/RDI/(R15) 97h VectorPath 2
XLATB/XLAT mem8 D7h VectorPath 5
XOR mreg8, reg8 30h 11-xxx-xxx DirectPath 1
XOR mem8, reg8 30h mm-xxx-xxx DirectPath 4
XOR mreg16/32/64, reg16/32/64 31h 11-xxx-xxx DirectPath 1
XOR mem16/32/64, reg16/32/64 31h mm-xxx-xxx DirectPath 4
XOR reg8, mreg8 32h 11-xxx-xxx DirectPath 1
XOR reg8, mem8 32h mm-xxx-xxx DirectPath 4
XOR reg16/32/64, mreg16/32/64 33h 11-xxx-xxx DirectPath 1
XOR reg16/32/64, mem16/32/64 33h mm-xxx-xxx DirectPath 4
XOR AL, imm8 34h DirectPath 1
XOR AX, imm16 35h DirectPath 1
XOR EAX, imm32 35h DirectPath 1
XOR RAX, imm32 (sign extended) 35h DirectPath 1
XOR mreg8, imm8 80h 11-110-xxx DirectPath 1
XOR mem8, v 80h mm-110-xxx DirectPath 4
XOR mreg16/32/64, imm16/32 81h 11-110-xxx DirectPath 1
XOR mem16/32/64, imm16/32 81h mm-110-xxx DirectPath 4
XOR mreg16/32/64, imm8 (sign extended) 83h 11-110-xxx DirectPath 1
XOR mem16/32/64, imm8 (sign extended) 83h mm-110-xxx DirectPath 4
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.