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Appendix C Instruction Latencies 315
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
PFRSQIT1 mmreg, mem64 0Fh, 0Fh A7h mm-xxx-xxx DirectPath FMUL 6
PFRSQRT mmreg1, mmreg2 0Fh, 0Fh 97h 11-xxx-xxx DirectPath FMUL 3
PFRSQRT mmreg, mem64 0Fh, 0Fh 97h mm-xxx-xxx DirectPath FMUL 5
PFSUB mmreg1, mmreg2 0Fh, 0Fh 9Ah 11-xxx-xxx DirectPath FADD 4
PFSUB mmreg, mem64 0Fh, 0Fh 9Ah mm-xxx-xxx DirectPath FADD 6
PFSUBR mmreg1, mmreg2 0Fh, 0Fh AAh 11-xxx-xxx DirectPath FADD 4
PFSUBR mmreg, mem64 0Fh, 0Fh AAh mm-xxx-xxx DirectPath FADD 6
PI2FD mmreg1, mmreg2 0Fh, 0Fh 0Dh 11-xxx-xxx DirectPath FADD 4
PI2FD mmreg, mem64 0Fh, 0Fh 0Dh mm-xxx-xxx DirectPath FADD 6
PMULHRW mmreg1, mmreg2 0Fh, 0Fh B7h 11-xxx-xxx DirectPath FMUL 3
PMULHRW mmreg1, mem64 0Fh, 0Fh B7h mm-xxx-xxx DirectPath FMUL 5
PREFETCH mem8 0Fh 0Dh mm-000-xxx DirectPath - ~ 1, 2
PREFETCHW mem8 0Fh 0Dh mm-001-xxx DirectPath - ~ 1, 2
Table 16. 3DNow!™ Technology Instructions (Continued)
Syntax
Encoding
Decode
type
FPU
pipe(s)
Latency Note
Prefix
byte(s)
imm8
ModRM
byte
Notes:
1. For the PREFETCH and PREFETCHW instructions, the mem8 value refers to an address in the 64-byte line to
be prefetched.
2. The byte listed in the column titled ‘imm8’ is actually the opcode byte.