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Appendix D AGP Considerations 345
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
Appendix D AGP Considerations
Fast write transactions are AGP data transfers that originate from processor-issued memory writes.
Frequently, the target of fast writes are graphics accelerators and involve:
• Memory-mapped I/O registers (for example, the command FIFO).
• Graphics (2D/3D) engines.
• DVD (motion compensation, sub-picture, etc.) engine registers.
• Frame buffer (render buffers, textures, etc.)
This appendix covers the following topics:
D.1 Fast-Write Optimizations
Fast-write transfers use the PCI addressing semantics but transfer data using the AGP transfer rates
(for example, 2x, 4x, or 8x) and AGP flow control between data blocks. The
AMD-8151™ HyperTransport™ AGP 3.0 graphics tunnel converts processor memory writes
(embedded in HyperTransport traffic) into fast-write transactions on the AGP bus. Fast writes offer an
alternative to having the processor place data in memory, and then having the AGP accelerator read
the data.
Fast-write transfers are generated to the accelerator with a transfer start address, and then transfer data
32 bits at a time (start_address + 0, start_address + 4, start_address + 8, and so on) until the entire
block has been transferred. In this sense, the data is sequential (as it is in DMA). Following are the
AGP bus characteristics:
• The AGP bus clock is 66 MHz.
• The AGP data width is 32 bits; at the 8x transfer rate, eight doublewords (32 bytes) can be
transferred per AGP clock.
Topic Page
Fast-Write Optimizations 345
Fast-Write Optimizations for Graphics-Engine Programming 346
Fast-Write Optimizations for Video-Memory Copies 349
Memory Optimizations 351
Memory Optimizations for Graphics-Engine Programming Using the DMA Model 352
Optimizations for Texture-Map Copies to AGP Memory 353
Optimizations for Vertex-Geometry Copies to AGP Memory 353