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250 Microarchitecture for AMD Athlon™ 64 and AMD Opteron™ Processors Appendix A
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
A.1 Key Microarchitecture Features
The AMD Athlon 64 and AMD Opteron processors include many features designed to improve
software performance. The internal design, or microarchitecture, of these processors provides the
following key features:
• Integrated DDR memory controller
• 64-Kbyte L1 instruction cache and 64-Kbyte L1 data cache
• On-chip L2 cache
• Instruction predecode and branch prediction during cache-line fills
• Decoupled decode/execution core
• Three-way AMD64 instruction decoding
• Dynamic scheduling and speculative execution
• Three-way integer execution
• Three-way address generation
• Three-way floating-point execution
• 3DNow!™ technology, MMX™, SSE, and SSE2 single-instruction multiple-data (SIMD)
instruction extensions
• Superforwarding
• Deep out-of-order integer and floating-point execution
• In 64-bit mode, eight additional XMM registers (for use with SSE and SSE2 instructions) and
eight additional general-purpose registers (GPRs)
• HyperTransport™ technology
Load-Store Unit 258
L2 Cache 259
Write-combining 260
Buses for AMD Athlon™ 64 and AMD Opteron™ Processor 260
Integrated Memory Controller 260
HyperTransport™ Technology Interface 260
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