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Appendix A Microarchitecture for AMD Athlon™ 64 and AMD Opteron™ Processors 251
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
A.2 Microarchitecture for AMD Athlon™ 64 and
AMD Opteron™ Processors
The AMD Athlon 64 and AMD Opteron processors implement the AMD64 instruction set by means
of micro-ops—simple fixed-length operations designed to include direct support for AMD64
instructions and adhere to the high-performance principles of fixed-length encoding, regularized
instruction fields, and a large register set. The enhanced microarchitecture enables higher processor
core performance and promotes straightforward extensibility for future designs.
A.3 Superscalar Processor
The AMD Athlon 64 and AMD Opteron processors are aggressive, out-of-order, three-way
superscalar AMD64 processors. They can fetch, decode, and issue up to three AMD64 instructions
per cycle with a centralized instruction control unit (ICU) and two independent instruction
schedulers—an integer scheduler and a floating-point scheduler. These two schedulers can
simultaneously issue up to nine micro-ops to the three general-purpose integer execution units
(ALUs), three address-generation units (AGUs), and three floating-point execution units. The
processors move integer instructions down the integer execution pipeline, which consists of the
integer scheduler and the ALUs, as shown in Figure 6 on page 252. Floating-point instructions are
handled by the floating-point execution pipeline, which consists of the floating-point scheduler and
the floating-point execution units.
A.4 Processor Block Diagram
A block diagram of the AMD Athlon 64 and AMD Opteron processors is shown in Figure 6 on
page 252.