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Appendix C Instruction Latencies 295
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
SAR mreg8, 1 D0h 11-111-xxx DirectPath 1
SAR mem8, 1 D0h mm-111-xxx DirectPath 4
SAR mreg16/32/64, 1 D1h 11-111-xxx DirectPath 1
SAR mem16/32/64, 1 D1h mm-111-xxx DirectPath 4
SAR mreg8, CL D2h 11-111-xxx DirectPath 1 3
SAR mem8, CL D2h mm-111-xxx DirectPath 4 3
SAR mreg16/32/64, CL D3h 11-111-xxx DirectPath 1 3
SAR mem16/32/64, CL D3h mm-111-xxx DirectPath 4 3
SBB mreg8, reg8 18h 11-xxx-xxx DirectPath 1
SBB mem8, reg8 18h mm-xxx-xxx DirectPath 4
SBB mreg16/32/64, reg16/32/64 19h 11-xxx-xxx DirectPath 1
SBB mem16/32/64, reg16/32/64 19h mm-xxx-xxx DirectPath 4
SBB reg8, mreg8 1Ah 11-xxx-xxx DirectPath 1
SBB reg8, mem8 1Ah mm-xxx-xxx DirectPath 4
SBB reg16/32/64, mreg16/32/64 1Bh 11-xxx-xxx DirectPath 1
SBB reg16/32/64, mem16/32/64 1Bh mm-xxx-xxx DirectPath 4
SBB AL, imm8 1Ch DirectPath 1
SBB AX, imm16 1Dh DirectPath 1
SBB EAX, imm32 1Dh DirectPath 1
SBB RAX, imm32 (sign extended) 1Dh DirectPath 1
SBB mreg8, imm8 80h 11-011-xxx DirectPath 1
SBB mem8, imm8 80h mm-011-xxx DirectPath 4
SBB mreg16/32/64, imm16/32 81h 11-011-xxx DirectPath 1
SBB mem16/32/64, imm16/32 81h mm-011-xxx DirectPath 4
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.