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296 Instruction Latencies Appendix C
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
SBB mreg16/32/64, imm8 (sign extended) 83h 11-011-xxx DirectPath 1
SBB mem16/32/64, imm8 (sign extended) 83h mm-011-xxx DirectPath 4
SCASB/SCAS mem8 AEh VectorPath 4 6
SCASD/SCAS mem32 AFh VectorPath 4 6
SCASQ/SCAS mem64 AFh VectorPath 4 6
SCASW/SCAS mem16 AFh VectorPath 4 6
SETA/SETNBE mem8 0Fh 97h mm-xxx-xxx DirectPath 3
SETA/SETNBE mreg8 0Fh 97h 11-xxx-xxx DirectPath 1
SETAE/SETNB/SETNC mem8 0Fh 93h mm-xxx-xxx DirectPath 3
SETAE/SETNB/SETNC mreg8 0Fh 93h 11-xxx-xxx DirectPath 1
SETB/SETC/SETNAE mem8 0Fh 92h mm-xxx-xxx DirectPath 3
SETB/SETC/SETNAE mreg8 0Fh 92h 11-xxx-xxx DirectPath 1
SETBE/SETNA mem8 0Fh 96h mm-xxx-xxx DirectPath 3
SETBE/SETNA mreg8 0Fh 96h 11-xxx-xxx DirectPath 1
SETE/SETZ mem8 0Fh 94h mm-xxx-xxx DirectPath 3
SETE/SETZ mreg8 0Fh 94h 11-xxx-xxx DirectPath 1
SETG/SETNLE mem8 0Fh 9Fh mm-xxx-xxx DirectPath 3
SETG/SETNLE mreg8 0Fh 9Fh 11-xxx-xxx DirectPath 1
SETGE/SETNL mem8 0Fh 9Dh mm-xxx-xxx DirectPath 3
SETGE/SETNL mreg8 0Fh 9Dh 11-xxx-xxx DirectPath 1
SETL/SETNGE mem8 0Fh 9Ch mm-xxx-xxx DirectPath 3
SETL/SETNGE mreg8 0Fh 9Ch 11-xxx-xxx DirectPath 1
SETLE/SETNG mem8 0Fh 9Eh mm-xxx-xxx DirectPath 3
SETLE/SETNG mreg8 0Fh 9Eh 11-xxx-xxx DirectPath 1
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.