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342 Instruction Latencies Appendix C
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
C.9 SSE3 Instructions
Table 20. SSE3 Instructions
Syntax
Encoding
Decode
type
FPU
pipe(s)
Latency
Throughput
Prefix
byte
First
byte
2nd
byte
ModRM byte
ADDSUBPD xmmreg1,
xmmreg2
66h 0Fh D0h 11-xxx-xxx Double FADD 5 1/2
ADDSUBPD xmmreg,
mem128
66h 0Fh D0h mm-xxx-xxx Double FADD 7 1/2
ADDSUBPS xmmreg1,
xmmreg2
F2h 0Fh D0h 11-xxx-xxx Double FADD 5 1/2
ADDSUBPS xmmreg,
mem128
F2h 0Fh D0h mm-xxx-xxx Double FADD 7 1/2
FISTTP [mem16int] DF mm-010-xxx DirectPath FSTORE 4
FISTTP [mem32int] DB mm-010-xxx DirectPath FSTORE 4
FISTTP [mem64int] DD mm-010-xxx DirectPath FSTORE 4
HADDPD xmmreg1,
xmmreg2
66h 0Fh 7Ch 11-xxx-xxx Double FADD 5 1/2
HADDPD xmmreg,
mem128
66h 0Fh 7Ch mm-xxx-xxx VectorPath FADD 6 1/2
HADDPS xmmreg1,
xmmreg2
F2h 0Fh 7Ch 11-xxx-xxx Double FADD 5 1/2
HADDPS xmmreg1,
mem128
F2h 0Fh 7Ch mm-xxx-xxx VectorPath FADD 6 1/2
HSUBPD xmmreg1,
xmmreg2
66h 0Fh 7Dh 11-xxx-xxx Double FADD 5 1/2
HSUBPD xmmreg1,
mem128
66h 0Fh 7Dh mm-xxx-xxx VectorPath FADD 6 1/2
HSUBPS xmmreg1,
xmmreg2
F2h 0Fh 7Dh 11-xxx-xxx Double FADD 5 1/2
HSUBPS xmmreg,
mem128
F2h 0Fh 7Dh mm-xxx-xxx VectorPath FADD 6 1/2
LDDQU xmmreg,
mem128
F2 0F F0 mm-xxx-xxx VectorPath 7 1/2
MOVDDUP xmmreg1,
xmmreg2
F2h 0Fh 12h 11-xxx-xxx Double FMUL 2 1/2
MOVDDUP xmmreg1,
mem64
F2h 0Fh 12h mm-xxx-xxx Double FMUL 4 1/2
MOVSHDUP xmmreg1,
xmmreg2
F3h 0Fh 16h 11-xxx-xxx Double FMUL 3 1/2