Filter
Top Products
328 Instruction Latencies Appendix C
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
CVTSD2SS xmmreg,
mem64
F2h 0Fh 5Ah mm-xxx-xxx Double FSTORE 9
CVTSI2SD xmmreg,
reg32/64
F2h 0Fh 2Ah 11-xxx-xxx Double FSTORE 11 1/1
CVTSI2SD xmmreg,
mem32/64
F2h 0Fh 2Ah mm-xxx-xxx DirectPath FSTORE 6 1/1
CVTSS2SD xmmreg1,
xmmreg2
F3h 0Fh 5Ah 11-xxx-xxx DirectPath FSTORE 2 1/1
CVTSS2SD xmmreg,
mem32
F3h 0Fh 5Ah mm-xxx-xxx DirectPath FSTORE 4 1/1
CVTSS2SI reg32/64,
xmmreg
F3h 0Fh 2Dh 11-xxx-xxx Double FSTORE 9
CVTSS2SI reg32/64,
mem32
F3h 0Fh 2Dh mm-xxx-xxx VectorPath ~ 10
CVTTPD2DQ xmmreg1,
xmmreg2
66h 0Fh E6h 11-xxx-xxx VectorPath ~ 8
CVTTPD2DQ xmmreg,
mem128
66h 0Fh E6h mm-xxx-xxx VectorPath ~ 10
CVTTPD2PI mmreg,
xmmreg
66h 0Fh 2Ch 11-xxx-xxx VectorPath ~ 8 1/2
CVTTPD2PI mmreg,
mem128
66h 0Fh 2Ch mm-xxx-xxx VectorPath ~ 10 1/2
CVTTPS2DQ xmmreg1,
xmmreg2
F3h 0Fh 5Bh 11-xxx-xxx Double FSTORE 5 1/2
CVTTPS2DQ xmmreg,
mem128
F3h 0Fh 5Bh mm-xxx-xxx Double FSTORE 7 1/2
CVTTSD2SI reg32/64,
xmmreg
F2h 0Fh 2Ch 11-xxx-xxx Double FSTORE 9 1/1
CVTTSD2SI reg32/64,
mem64
F2h 0Fh 2Ch mm-xxx-xxx VectorPath FADD/
FMUL/
FSTORE
10 1/1
CVTTSS2SI reg32/64,
xmmreg
F3h 0Fh 2Ch 11-xxx-xxx Double FSTORE 9
CVTTSS2SI reg32/64,
mem32
F3h 0Fh 2Ch mm-xxx-xxx VectorPath ~ 10
Table 19. SSE2 Instructions (Continued)
Syntax
Encoding
Decode
type
FPU
pipe(s)
Latency
Throughput
Note
Prefix
byte
First
byte
2nd
byte
ModRM byte
Notes:
1. The low half of the result is available one cycle earlier than listed.
2. This is the execution latency for the instruction. The time to complete the external write depends on the memory
speed and the hardware implementation.