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300 Instruction Latencies Appendix C
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
SUB RAX, imm32 (sign extended) 2Dh DirectPath 1
SUB mreg8, imm8 80h 11-101-xxx DirectPath 1
SUB mem8, imm8 80h mm-101-xxx DirectPath 4
SUB mreg16/32/64, imm16/32 81h 11-101-xxx DirectPath 1
SUB mem16/32/64, imm16/32 81h mm-101-xxx DirectPath 4
SUB mreg16/32/64, imm8 (sign extended) 83h 11-101-xxx DirectPath 1
SUB mem16/32/64, imm8 (sign extended) 83h mm-101-xxx DirectPath 4
SYSCALL 0Fh 05h VectorPath 27
SYSENTER 0Fh 34h VectorPath ~
SYSEXIT 0Fh 35h VectorPath ~
SYSRET 0Fh 07h VectorPath 35
TEST mreg8, reg8 84h 11-xxx-xxx DirectPath 1
TEST mem8, reg8 84h mm-xxx-xxx DirectPath 4
TEST mreg16/32/64, reg16/32/64 85h 11-xxx-xxx DirectPath 1
TEST mem16/32/64, reg16/32/64 85h mm-xxx-xxx DirectPath 4
TEST AL, imm8 A8h DirectPath 1
TEST AX/EAX/RAX, imm16/32 A9h DirectPath 1
TEST mreg8, imm8 F6h 11-000-xxx DirectPath 1
TEST mem8, imm8 F6h mm-000-xxx DirectPath 4
TEST mreg16/32/64, imm16/32 F7h 11-000-xxx DirectPath 1
TEST mem16/32/64, imm16/32 F7h mm-000-xxx DirectPath 4
VERR mreg16 0Fh 00h 11-100-xxx VectorPath 11
VERR mem16 0Fh 00h mm-100-xxx VectorPath 11
VERW mreg16 0Fh 00h 11-101-xxx VectorPath 11
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.