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Appendix B Implementation of Write-Combining 263
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
Appendix B Implementation of
Write-Combining
This appendix describes the memory write-combining feature implemented in the AMD Athlon™ 64
and AMD Opteron™ processors. Write-combining is the merging of multiple memory write cycles
that target locations within the address range of a write buffer.
The AMD Athlon 64 and AMD Opteron processors support the memory type range register (MTRR)
and the page attribute table (PAT) extensions, which allow software to define ranges of memory as
either writeback (WB), write-protected (WP), writethrough (WT), uncacheable (UC), or write-
combining (WC).
Defining the memory type for a range of memory as WC or WT allows the processor to conditionally
combine data from multiple write cycles that are addressed within this range into a merge buffer.
Merging multiple write cycles into a single write cycle reduces processor bus utilization and
processor stalls. Write combining buffers are also used for streaming store instructions such as
MOVNTQ and MOVNTI. See “Streaming-Store/Non-Temporal Instructions” on page 112.
This appendix covers the following topics:
B.1 Write-Combining Definitions and Abbreviations
This appendix uses the following definitions and abbreviations:
• MTRR—Memory type range register
• PAT—Page attribute table
• UC—Uncacheable memory type
• WC—Write-combining memory type
• WT—Writethrough memory type
• WP—Write-protected memory type
Topic Page
Write-Combining Definitions and Abbreviations 263
Programming Details 264
Write-combining Operations 264
Sending Write-Buffer Data to the System 266
Write-Combining Optimization on Revision D and E AMD Athlon™ 64 and AMD Opteron™
Processors
266