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278 Instruction Latencies Appendix C
25112 Rev. 3.06 September 2005
Software Optimization Guide for AMD64 Processors
CMOVBE/CMOVNA reg16/32/64,
mem16/32/64
0Fh 46h mm-xxx-xxx DirectPath 4
CMOVBE/CMOVNA reg16/32/64, reg16/32/64 0Fh 46h 11-xxx-xxx DirectPath 1
CMOVE/CMOVZ reg16/32/64, mem16/32/64 0Fh 44h mm-xxx-xxx DirectPath 4
CMOVE/CMOVZ reg16/32/64, reg16/32/64 0Fh 44h 11-xxx-xxx DirectPath 1
CMOVG/CMOVNLE reg16/32/64,
mem16/32/64
0Fh 4Fh mm-xxx-xxx DirectPath 4
CMOVG/CMOVNLE reg16/32/64, reg16/32/64 0Fh 4Fh 11-xxx-xxx DirectPath 1
CMOVGE/CMOVNL reg16/32/64,
mem16/32/64
0Fh 4Dh mm-xxx-xxx DirectPath 4
CMOVGE/CMOVNL reg16/32/64, reg16/32/64 0Fh 4Dh 11-xxx-xxx DirectPath 1
CMOVL/CMOVNGE reg16/32/64,
mem16/32/64
0Fh 4Ch mm-xxx-xxx DirectPath 4
CMOVL/CMOVNGE reg16/32/64, reg16/32/64 0Fh 4Ch 11-xxx-xxx DirectPath 1
CMOVLE/CMOVNG reg16/32/64,
mem16/32/64
0Fh 4Eh mm-xxx-xxx DirectPath 4
CMOVLE/CMOVNG reg16/32/64, reg16/32/64 0Fh 4Eh 11-xxx-xxx DirectPath 1
CMOVNE/CMOVNZ reg16/32/64,
mem16/32/64
0Fh 45h mm-xxx-xxx DirectPath 4
CMOVNE/CMOVNZ reg16/32/64, reg16/32/64 0Fh 45h 11-xxx-xxx DirectPath 1
CMOVNO reg16/32/64, mem16/32/64 0Fh 41h mm-xxx-xxx DirectPath 4
CMOVNO reg16/32/64, reg16/32/64 0Fh 41h 11-xxx-xxx DirectPath 1
CMOVNP/CMOVPO reg16/32/64,
mem16/32/64
0Fh 4Bh mm-xxx-xxx DirectPath 4
CMOVNP/CMOVPO reg16/32/64, reg16/32/64 0Fh 4Bh 11-xxx-xxx DirectPath 1
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.