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Appendix C Instruction Latencies 343
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
MOVSHDUP xmmreg,
mem128
F3h 0Fh 16h mm-xxx-xxx Double FMUL 5 1/2
MOVSLDUP xmmreg1,
xmmreg2
F3h 0Fh 12h 11-xxx-xxx Double FMUL 3 1/2
MOVSLDUP xmmreg1,
mem128
F3h 0Fh 12h mm-xxx-xxx Double FMUL 5 1/2
Table 20. SSE3 Instructions (Continued)
Syntax
Encoding
Decode
type
FPU
pipe(s)
Latency
Throughput
Prefix
byte
First
byte
2nd
byte
ModRM byte