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Appendix C Instruction Latencies 325
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
UNPCKLPS xmmreg1,
xmmreg2
0Fh 14h 11-xxx-xxx Double FMUL 3 3
UNPCKLPS xmmreg,
mem128
0Fh 14h mm-xxx-xxx Double FMUL 5 3
XORPS xmmreg1,
xmmreg2
0Fh 57h 11-xxx-xxx Double FMUL 3 1
XORPS xmmreg,
mem128
0Fh 57h mm-xxx-xxx Double FMUL 5 1
Table 18. SSE Instructions (Continued)
Syntax
Encoding
Decode
type
FPU pipe(s) Latency Note
Prefix
byte
First
byte
2nd
byte
ModRM byte
Notes:
1. The low half of the result is available one cycle earlier than listed.
2. The second latency value indicates when the low half of the result becomes available.
3. The high half of the result is available one cycle earlier than listed.
4. The latency listed is the absolute minimum, while average latencies may be higher and are a function of internal
pipeline conditions.
5. For the PREFETCHNTA/T0/T1/T2 instructions, the mem8 value refers to an address in the 64-byte line to be
prefetched.
6. The 8-clock latency is only visible to younger stores that need to do an external write. The 2-clock latency is
visible to the other stores and instructions.
7. This is the execution latency for the instruction. The time to complete the external write depends on the memory
speed and the hardware implementation.