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Appendix C Instruction Latencies 281
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
DAS 2Fh VectorPath 7
DEC AX/EAX 48h DirectPath 1 8
DEC BP/EBP 4Dh DirectPath 1 8
DEC BX/EBX 4Bh DirectPath 1 8
DEC CX/ECX 49h DirectPath 1 8
DEC DI/EDI 4Fh DirectPath 1 8
DEC DX/EDX 4Ah DirectPath 1 8
DEC SI/ESI 4Eh DirectPath 1 8
DEC SP/ESP 4Ch DirectPath 1 8
DEC mem8 FEh mm-001-xxx DirectPath 4
DEC mreg8 FEh 11-001-xxx DirectPath 1
DEC mem16/32/64 FFh mm-001-xxx DirectPath 4
DEC mreg16/32/64 FFh 11-001-xxx DirectPath 1
DIV mem8 F6h mm-110-xxx VectorPath 16
DIV mreg8 F6h 11-110-xxx VectorPath 16
DIV mem16/32/64 F7h mm-110-xxx VectorPath 23/39/
71
DIV mreg16/32/64 F7h 11-110-xxx VectorPath 23/39/
71
ENTER C8h VectorPath 14/17/
19/21
5
IDIV mreg8 F6h 11-111-xxx VectorPath 18
IDIV mem8 F6h mm-111-xxx VectorPath 19
IDIV mreg16/32/64 F7h 11-111-xxx VectorPath 26/42/
74
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.