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Appendix A Microarchitecture for AMD Athlon™ 64 and AMD Opteron™ Processors 255
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
L1 Data TLB Specifications
Table 9 provides the specifications of the L1 data TLB for various AMD processors.
Table 9. L1 Data TLB Specifications
L2 TLB Specifications
Table 10 provides the specifications on the L2 TLB for various AMD processors.
A.10 L1 Data Cache
The L1 data cache contains two 64-bit ports. It is a write-allocate and writeback cache that uses a
least-recently-used replacement policy. It is divided into eight banks, each eight bytes wide. In
addition, the L1 cache supports the MOESI (Modified, Owner, Exclusive, Shared, and Invalid) cache-
coherency protocol and data parity.
Table 8. L1 Instruction TLB Specifications
Number of Entries
Processor Name Family Model Associativity
2-Mbyte Pages
1
4-Kbyte Pages
AMD Athlon™ XP Processor 6 6 Full 8 16
AMD Athlon™ 64 Processor 15 All Full 8 32
AMD Opteron™ Processor 15 All Full 8 32
Note:
1. The number of entries available for 4-Mbyte pages is one-half this value (4-Mbyte pages require two 2-Mbyte
entries).
Number of Entries
Processor Name Family Model Associativity
2-Mbyte pages
1
4-Kbyte pages
AMD Athlon™ XP Processor 6 6 Full 8 32
AMD Athlon™ 64 Processor 15 All Full 8 32
AMD Opteron™ Processor 15 All Full 8 32
Note:
1. The number of entries available for 4-Mbyte pages is one-half this value (4-Mbyte pages require two 2-Mbyte
entries).
Table 10. L2 TLB Specifications by Processor
Processor Name Family Model Associativity Number of Entries (4-Kbyte Pages)
AMD Athlon™ XP Processor 6 6 4 ways 256
AMD Athlon™ 64 Processor 15 All 4 ways 512
AMD Opteron™ Processor 15 All 4 ways 512