Filter
Top Products
Appendix C Instruction Latencies 289
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
MOVZX reg16/32/64, mreg8 0Fh B6h 11-xxx-xxx DirectPath 1
MOVZX reg16/32/64, mem8 0Fh B6h mm-xxx-xxx DirectPath 4
MOVZX reg32/64, mreg16 0Fh B7h 11-xxx-xxx DirectPath 1
MOVZX reg32/64, mem16 0Fh B7h mm-xxx-xxx DirectPath 4
MUL mreg8 F6h 11-100-xxx DirectPath 3
MUL AL, mem8 F6h mm-100-xx DirectPath 6
MUL mreg16 F7h 11-100-xxx VectorPath 4
MUL mem16 F7h mm-100-xxx VectorPath 7
MUL mreg32 F7h 11-100-xxx Double 3
MUL mem32 F7h mm-100-xx Double 6
MUL mreg64 F7h 11-100-xxx Double 5
MUL mem64 F7h mm-100-xx Double 8
NEG mreg8 F6h 11-011-xxx DirectPath 1
NEG mem8 F6h mm-011-xxx DirectPath 4
NEG mreg16/32/64 F7h 11-011-xxx DirectPath 1
NEG mem16/32/64 F7h mm-011-xx DirectPath 4
NOP (XCHG EAX, EAX) 90h DirectPath ~0 5
NOT mreg8 F6h 11-010-xxx DirectPath 1
NOT mem8 F6h mm-010-xx DirectPath 4
NOT mreg16/32/64 F7h 11-010-xxx DirectPath 1
NOT mem16/32/64 F7h mm-010-xx DirectPath 4
OR mreg8, reg8 08h 11-xxx-xxx DirectPath 1
OR mem8, reg8 08h mm-xxx-xxx DirectPath 4
OR mreg16/32/64, reg16/32/64 09h 11-xxx-xxx DirectPath 1
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.