AMD 250 Computer Hardware User Manual


 
Appendix C Instruction Latencies 277
Software Optimization Guide for AMD64 Processors
25112 Rev. 3.06 September 2005
CALL mem16/32/64 (near, indirect) FFh mm-010-xxx VectorPath 4
CALL mreg16/32/64 (near, indirect) FFh 11-010-xxx VectorPath 4
CALL mem16:16/32 (far, indirect) FFh 11-011-xxx VectorPath ~
CALL pntr16:16/32 (far, direct, no CPL
change)
9Ah VectorPath 33
CALL pntr16:16/32 (far, direct, CPL change) 9Ah VectorPath 150
CBW/CWDE/CDQE 98h DirectPath 1
CLC F8h DirectPath 1
CLD FCh DirectPath 1
CLFLUSH 0Fh AEh mm-111-xx DirectPath ~
CLI FAh VectorPath 4
CLTS 0Fh 06h VectorPath 10
CMC F5h DirectPath 1
CMOVA/CMOVNBE reg16/32/64,
mem16/32/64
0Fh 47h mm-xxx-xxx DirectPath 4
CMOVA/CMOVNBE reg16/32/64, reg16/32/64 0Fh 47h 11-xxx-xxx DirectPath 1
CMOVAE/CMOVNB/CMOVNC reg16/32/64,
mem16/32/64
0Fh 43h mm-xxx-xxx DirectPath 4
CMOVAE/CMOVNB/CMOVNC reg16/32/64,
reg16/32/64
0Fh 43h 11-xxx-xxx DirectPath 1
CMOVB/CMOVC/CMOVNAE reg16/32/64,
mem16/32/64
0Fh 42h mm-xxx-xxx DirectPath 4
CMOVB/CMOVC/CMOVNAE reg16/32/64,
reg16/32/64
0Fh 42h 11-xxx-xxx DirectPath 1
Table 13. Integer Instructions (Continued)
Syntax
Encoding
Decode
type
Latency Note
First
byte
Second
byte
ModRM
byte
Notes:
1. Static timing assumes a predicted branch.
2. Store operation also updates ESP—the new register value is available one clock earlier than the specified
latency.
3. The clock count, regardless of the number of shifts or rotates, as determined by CL or imm8.
4. LEA instructions have a latency of 1 when there are two source operands (as in the case of the base + index
form LEA EAX, [EDX+EDI]). Forms with a scale or more than two source operands will have a latency of 2 (LEA
EAX, [EBX+EBX*8]).
5. These instructions have an effective latency as shown. They map to internal NOPs that can be issued at a rate of
three per cycle but do not occupy execution resources.
6. The latency of repeated string instructions can be found in “Latency of Repeated String Instructions” on
page 167.
7. The first latency value is for 32-bit mode. The second is for 64-bit mode.
8. This opcode is used as a REX prefix in 64-bit mode.