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5.7.2DDR2MemoryController
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
TheDDR2/mDDRMemoryControllerisadedicatedinterfacetoDDR2/mDDRSDRAM.Itsupports
JESD79D-2AstandardcompliantDDR2SDRAMdevicesandcompliantMobileDDRSDRAMdevices.
DDR2/mDDRSDRAMplaysakeyroleinaDM355-basedsystem.Suchasystemisexpectedtorequire
asignificantamountofhigh-speedexternalmemoryforallofthefollowingfunctions:
•Bufferingofinputimagedatafromsensorsorvideosources
•Intermediatebufferingforprocessing/resizingofimagedataintheVPFE
•NumerousOSDdisplaybuffers
•IntermediatebufferingforlargerawBayerdataimagefileswhileperformingimageprocessing
functions
•Bufferingforintermediatedatawhileperformingvideoencodeanddecodefunctions
•StorageofexecutablecodefortheARM
TheDDR2/mDDRMemoryControllersupportsthefollowingfeatures:
•JESD79D-2AstandardcompliantDDR2SDRAM
•MobileDDRSDRAM
•256MBytememoryspace
•Databuswidth16bits
•CASlatencies:
–DDR2:2,3,4,and5
–mDDR:2and3
•Internalbanks:
–DDR2:1,2,4,and8
–mDDR:1,2,and4
•Burstlength:8
•Bursttype:sequential
•1CSsignal
•Pagesizes:256,512,1024,and2048
•SDRAMautoinitialization
•Self-refreshmode
•Partialarrayself-refresh(formDDR)
•Powerdownmode
•Prioritizedrefresh
•Programmablerefreshrateandbacklogcounter
•Programmabletimingparameters
•Littleendian
FordetailsontheDDR2MemoryController,refertotheDDR/mDDRPeripheralReferenceGuide.
5.7.2.1DDR2/mDDRMemoryControllerElectricalData/Timing
TIonlysupportsDDR2/mDDRboarddesignsthatfollowtheguidelinesdescribedintheapplicationnote
titledTMS320DM355DDR2/mDDRBoardDesignApplicationNote.Refertothisapplicationnotefor
informationonboarddesignrecommendationsandguidelinesforDDR2andmDDR.
PeripheralInformationandElectricalSpecifications 112SubmitDocumentationFeedback