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PRODUCT PREVIEW
3.2.4TightlyCoupledMemory(TCM)
3.2.5AdvancedHigh-performanceBus(AHB)
3.2.6EmbeddedTraceMacrocell(ETM)andEmbeddedTraceBuffer(ETB)
3.3MemoryMapping
3.3.1ARMInternalMemories
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
Thewritebufferisusedforallwritestoanoncachablebufferableregion,write-throughregionandwrite
missestoawrite-backregion.AseparatebufferisincorporatedintheDcacheforholdingwrite-backfor
cachelineevictionsorcleaningofdirtycachelines.Themainwritebufferhas16-worddatabufferanda
four-addressbuffer.TheDcachewrite-backhaseightdatawordentriesandasingleaddressentry.
ARMinternalRAMisprovidedforstoringreal-timeandperformance-criticalcode/dataandtheInterrupt
Vectortable.ARMinternalROMenablesnon-AEMIFbootoptions,suchasNAND,UART,andHPI.The
RAMandROMmemoriesinterfacedtotheARM926EJ-Sviathetightlycoupledmemoryinterfacethat
providesforseparateinstructionanddatabusconnections.SincetheARMTCMdoesnotallow
instructionsontheD-TCMbusordataontheI-TCMbus,anarbiterisincludedsothatbothdataand
instructionscanbestoredintheinternalRAM/ROM.ThearbiteralsoallowsaccessestotheRAM/ROM
fromextra-ARMsources(e.g.,EDMAorothermasters).TheARM926EJ-Shasbuilt-inDMAsupportfor
directaccessestotheARMinternalmemoryfromanon-ARMmaster.Becauseofthetime-criticalnature
oftheTCMlinktotheARMinternalmemory,allaccessesfromnon-ARMdevicesaretreatedasDMA
transfers.
InstructionandDataaccessesaredifferentiatedviaaccessingdifferentmemorymapregions,withthe
instructionregionfrom0x0000through0x7FFFanddatafrom0x10000through0x17FFF.Placingthe
instructionregionat0x0000isnecessarytoallowtheARMInterruptVectortabletobeplacedat0x0000,
asrequiredbytheARMarchitecture.Theinternal32-KBRAMissplitintotwophysicalbanksof16KB
each,whichallowssimultaneousinstructionanddataaccessestobeaccomplishedifthecodeanddata
areinseparatebanks.
TheARMSubsystemusestheAHBportoftheARM926EJ-StoconnecttheARMtotheconfigurationbus
andtheexternalmemories.ArbitersareemployedtoarbitrateaccesstotheseparateD-AHBandI-AHB
bytheconfigurationbusandtheexternalmemoriesbus.
Tosupportreal-timetrace,theARM926EJ-Sprocessorprovidesaninterfacetoenableconnectionofan
EmbeddedTraceMacrocell(ETM).TheARM926ES-JSubsysteminDM355alsoincludestheEmbedded
TraceBuffer(ETB).TheETMconsistsoftwoparts:
•TracePortprovidesreal-timetracecapabilityfortheARM9.
•Triggeringfacilitiesprovidetriggerresources,whichincludeaddressanddatacomparators,counter,
andsequencers.
TheDM355traceportisnotpinnedoutandisinsteadonlyconnectedtotheEmbeddedTraceBuffer.The
ETBhasa4KBbuffermemory.ETBenableddebugtoolsarerequiredtoread/interpretthecapturedtrace
data.
TheARMmemorymapisshowninTable2-2andTable2-3.Thissectiondescribesthememoriesand
interfaceswithintheARM'smemorymap.
TheARMhasaccesstothefollowingARMinternalmemories:
•32KBARMInternalRAMonTCMinterface,logicallyseparatedintotwo16KBpagestoallow
simultaneousaccessonanygivencycleifthereareseparateaccessesforcode(I-TCMbus)anddata
(D-TCM)tothedifferentmemoryregions.
•8KBARMInternalROM
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