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PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
7,9
HD/VD
CI[7:0]/YI[7:0]/
CCD[13:0]
8,10
11,13
12,14
5
6
C_WE/C_FIELD
PCLK
(PositiveEdgeClocking)
15
16
23
24
CI[7:0]/YI[7:0]/
CCD[13:0]
C_WE/C_FIELD
PCLK
(PositiveEdgeClocking)
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
Figure5-24.VPFE(CCD)SlaveModeInputDataTiming
Table5-19.TimingRequirementsforVPFE(CCD)MasterMode
(1)
(seeFigure5-25)
DM355
NO.UNIT
MINMAX
15t
su(CCDV-PCLK)
Setuptime,CCDvalidbeforePCLKedge3ns
16t
h(PCLK-CCDV)
Holdtime,CCDvalidafterPCLKedge2ns
23t
su(CWEV-PCLK)
Setuptime,C_WEvalidbeforePCLKedge3ns
24t
h(PCLK-CWEV)
Holdtime,C_WEvalidafterPCLKedge2ns
(1)TheVPFEmaybeconfiguredtooperateineitherpositiveornegativeedgeclockingmode.Wheninpositiveedgeclockingmodethe
risingedgeofPCLKisreferenced.WheninnegativeedgeclockingmodethefallingedgeofPCLKisreferenced.
Figure5-25.VPFE(CCD)MasterModeInputDataTiming
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