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3.11.2PLLConfiguration
3.11.3PowerDomainandModuleStateConfiguration
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
AfterPOR,warmreset,andmaxreset,thePLLsandclocksaresettotheirdefaultconfigurations.The
PLLsareinbypassmodeanddisabledbydefault.ThismeansthattheinputreferenceclockatMXI1
(typically24MHz)drivesthechipafterreset.Formoreinformationondeviceclocking,seeSection3.5
andSection3.6.ThedefaultstateofthePLLsisreflectedinthedefaultstateoftheregisterbitsinthe
PLLCregisters.ReferthetheARMSubsystemUser'sGuideforPLLCregisterdescriptions.
Onlyasubsetofmodulesareenabledafterresetbydefault.Table3-16showswhichmodulesare
enabledafterreset.Table3-16asshowsthatthefollowingmodulesareenableddependingonthe
sampledstateofthedeviceconfigurationpins:EDMA(CCandTC0),AEMIF,MMC/SD0,UART0,and
Timer0.Forexample,UART0isenabledafterresetwhenthedeviceconfigurationpins(BTSEL[1:0]=11-
EnableUART)selectUARTbootmode.FormoreinformationonmoduleconfigurationrefertotheARM
SubsystemUser'sGuide.
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