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2.4.4DDRMemoryInterface
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
Table2-9.AsynchronousEMIF/NAND/OneNANDTerminalFunctions(continued)
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAMENO.
AsyncEMIF:Lowestnumberedchipselect.Canbeprogrammedtobeusedfor
EM_CE0/standardasynchronousmemories(example:flash),OneNAND,orNAND
J16I/O/ZV
DD
GIO037memory.UsedforthedefaultbootandROMbootmodes.
GIO:GIO[037]
AsyncEMIF:Secondchipselect.Canbeprogrammedtobeusedforstandard
EM_CE1/
G19I/O/ZV
DD
asynchronousmemories(example:flash),OneNAND,orNANDmemory.
GIO036
GIO:GIO[036]
AsyncEMIF:WriteEnable
EM_WE/
J15I/O/ZV
DD
NAND/SM/xD:WE(WriteEnable)output
GIO035
GIO:GIO[035]
AsyncEMIF:OutputEnable
EM_OE/
F19I/O/ZV
DD
NAND/SM/xD:RE(ReadEnable)output
GIO034
GIO:GIO[034]
AsyncEMIF:AsyncWAIT
EM_WAIT/
G18I/O/ZV
DD
NAND/SM/xD:RDY/BSYinput
GIO033
GIO:GIO[033]
EM_ADV/OneNAND:AddressvaliddetectforOneNANDinterface
H16I/O/ZV
DD
GIO032GIO:GIO[032]
EM_CLK/OneNAND:ClockforOneNANDflashinterface
E19I/O/ZV
DD
GIO031GIO:GIO[031]
TheDDREMIFsupportsDDR2andmobileDDR.
Table2-10.DDRTerminalFunctions
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAMENO.
DDR_CLKW9I/O/ZV
DD_DDR
DDRDataClock
DDR_CLKW8I/O/ZV
DD_DDR
DDRComplementaryDataClock
DDR_RAST6I/O/ZV
DD_DDR
DDRRowAddressStrobe
DDR_CASV9I/O/ZV
DD_DDR
DDRColumnAddressStrobe
DDR_WEW10I/O/ZV
DD_DDR
DDRWriteEnable
DDR_CST8I/O/ZV
DD_DDR
DDRChipSelect
DDR_CKEV10I/O/ZV
DD_DDR
DDRClockEnable
DDR_DQM[
Datamaskoutputs:
U15I/O/ZV
DD_DDR
1]
•DQM0-ForDDR_DQ[7:0]
DDR_DQM[
T12I/O/ZV
DD_DDR
•DQM1-ForDDR_DQ[15:8]
0]
DDR_DQS[Datastrobeinput/outputsforeachbyteofthe16-bitdatabususedto
V15I/O/ZV
DD_DDR
1]synchronizethedatatransfers.OutputtoDDRwhenwritingandinputswhen
reading.
DDR_DQS[
•DQS1-ForDDR_DQ[15:8]
V12I/O/ZV
DD_DDR
0]
•DQS0-ForDDR_DQ[7:0]
DDR_BA[2]V8I/O/ZV
DD_DDR
Bankselectoutputs.Twoarerequiredfor1GbDDR2memories.
DDR_BA[1]U7I/O/ZV
DD_DDR
Bankselectoutputs.Twoarerequiredfor1GbDDR2memories.
DDR_BA[0]U8I/O/ZV
DD_DDR
Bankselectoutputs.Twoarerequiredfor1GbDDR2memories.
DDR_A13U6I/O/ZV
DD_DDR
DDRAddressBusbit13
DDR_A12V7I/O/ZV
DD_DDR
DDRAddressBusbit12
DDR_A11W7I/O/ZV
DD_DDR
DDRAddressBusbit11
(1)I=Input,O=Output,Z=Highimpedance,S=Supplyvoltage,GND=Ground,A=Analogsignal.
(2)SpecifiestheoperatingI/Osupplyvoltageforeachsignal.SeeSection5.3,PowerSuppliesformoredetail.
(3)PD=pull-down,PU=pull-up.(Topullupasignaltotheoppositesupplyrail,a1kΩresistorshouldbeused.)
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